During low-power modes (when fSW < fSMP(max)), the device disables the internal pull-up on the SD pin. This action allows the pin voltage to fall to GND, and the SD pin then functions as a transient wake-up input. In this case, if the pin rises above the wake threshold while the device is in low-power sleep mode, the device wakes and starts PWM pulses immediately. This feature is useful for applications that require a faster response to load transients from zero or near-zero load, where a wake-up signal can be appropriately coupled to the SD pin from the secondary side.
Figure 38 describes a typical secondary-side wake circuit and coupling of the wake signal to the controller on the primary side. This circuit uses a TL103W component which is an integrated reference plus two op-amps in a convenient SOIC-8 package. Both op-amps are connected to the same internal 2.5-V TL431 type reference, with a 3-resistor divider chain allowing each op-amp to monitor a different level. The upper op-amp output is low as long as the device is regulating the output voltage normally. If a sufficiently large load transient occurs while the primary-side controller is in sleep mode, the output voltage drops below a transient wake level. The upper op-amp output goes high, driving current through the low-cost wake signal opto-coupler. On the primary side, the wake opto-coupler pulls up the SD pin above the wake threshold and forces PWM switching as a reaction to the load transient.
The lower op-amp section monitors the output voltage and its output goes low only when the output voltage is above a minimum enable threshold for the secondary-side wake-up monitor. This action is necessary so that under certain conditions, such as a start-up sequence or short-circuit condition (when the output voltage is already below the transient wake level) that the secondary-side circuit does not continually drive the wake opto-coupler, which could activate an SD pin fault during pin-fault checking at start-up.