Because the output voltage feedback is inherently a sampled signal obtained from the bias winding, the internal voltage control loop is most naturally implemented digitally. The internal control loop implements the equivalent of a PID loop in digital form. Because the output can be sampled only at certain intervals in each switching cycle, the sample rate is naturally tied to the switching frequency, and the sample rate increases with increasing frequency. However, the device clamps the sample rate at a normalized maximum rate, fSMP(max). But because the device must always synchronize to the next available switching cycle to obtain a new sample of the output voltage, the effective sample rate varies somewhat around this value.
The digital control loop compensator block diagram is shown in Figure 29. A new sample of output voltage is supplied to the compensator at the normalized maximum clock rate (fSMP(max)) , or fSW, whichever is lower. An updated output voltage demand signal, yk, is produced at the same clock rate. This voltage loop demand represents the required operating point on the modulator curves to keep the output voltage in regulation. The modulator sets the appropriate switching frequency and peak current demand depending on the load power.
The control loop PID gain factors are internally fixed values, optimized for flyback power stages in the range between 20 W and 130 W. The loop is designed to work with magnetizing inductance values in the range between 200 µH and 1500 µH. Assuming that the output capacitance value is chosen based on required ripple current rating, then loop stability is not a problem. Adding extra output capacitance does not degrade the loop performance and the resulting extra output hold-up improves transient response.
The Typical Application section includes gain-phase measurements taken using the 65-W UCC28630EVM-572 evaluation module.