SLUSBL5A February   2015  – June 2019 UCC28730

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Zero-Power Input Consumption at No-Load
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 HV (High Voltage Startup)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CBC (Cable Compensation)
        6. 7.3.1.6 VS (Voltage Sense)
        7. 7.3.1.7 CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-By Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CVDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty-Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ω
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 DC Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in Volts
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1.6 VS (Voltage Sense)

The VS pin connects to a resistor-divider from the auxiliary winding to ground and is used to sense input voltage, output voltage, event timing, and Wait-state wake-up signaling. The auxiliary voltage waveform is sampled at the end of the transformer secondary current demagnetization time to provide an accurate representation of the output voltage. The waveform on the VS pin determines the timing information to achieve valley-switching, and the timing to control the duty-cycle of the transformer secondary current when in Constant-Current Mode. Avoid placing a filter capacitor on this input which interferes with accurate sensing of this waveform.

During the MOSFET on-time, this pin also senses VS current generated through RS1 by the reflected bulk-capacitor voltage to provide for AC-input Run and Stop thresholds, and to compensate the current-sense threshold across the AC-input range. For the AC-input Run/Stop function, the Run threshold on VS is 225 µA and the Stop threshold is 80 µA.

At the end of off-time demagnetization, the reflected output voltage is sampled at this pin to provide regulation and overvoltage protection. The values for the auxiliary voltage-divider upper-resistor, RS1, and lower-resistor, RS2, are determined by Equation 2 and Equation 3.

Equation 2. UCC28730 qu1_lusbl5.gif

where

  • VIN(run) is the target AC RMS voltage to enable turn-on of the controller (Run) (in case of DC input, leave out the √2 term in the equation),
  • IVSL(run) is the Run-threshold for the current pulled out of the VS pin during the switch on-time (see Electrical Characteristics),
  • NPA is the transformer primary-to-auxiliary turns-ratio.
Equation 3. UCC28730 qu2_lusbl5.gif

where

  • VOCV is the converter regulated output voltage,
  • VF is the output rectifier forward drop at near-zero current,
  • NAS is the transformer auxiliary-to-secondary turns-ratio,
  • RS1 is the VS divider high-side resistance,
  • VVSR is the CV regulating level at the VS input (see Electrical Characteristics).

When the UCC28730 is operating in the Wait state, the VS input is receptive to a wake-up signal superimposed upon the auxiliary winding waveform after the waveform meets either of two qualifying conditions. A high-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds VWU(high) (2 V) provided that any voltage at VS has been continuously below VWU(high) for the wake-up qualification delay tWDLY (8.5 us) after the demagnetization interval. A low-level wake-up signal is considered to be detected if the amplitude at the VS input exceeds VWU(low) (57 mV) provided that any voltage at VS has been continuously below VWU(low) for the wake-up qualification delay tWDLY (8.5 us) after the demagnetization interval. The high-level threshold accommodates signals generated by a low-impedance secondary-side driver while the low-level threshold detects signals generated by a high-impedance driver.