SLAS950A May   2013  – June 2015 DAC7562-Q1 , DAC7563-Q1 , DAC8162-Q1 , DAC8163-Q1 , DAC8562-Q1 , DAC8563-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Tables of Graphs
      2. 7.7.2 Internal Reference
      3. 7.7.3 DAC at AVDD = 5.5 V
      4. 7.7.4 Typical Characteristics: DAC at AVDD = 3.6 V
      5. 7.7.5 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC)
        1. 8.3.1.1 Resistor String
        2. 8.3.1.2 Output Amplifier
      2. 8.3.2 Internal Reference
      3. 8.3.3 Power-On Reset
        1. 8.3.3.1 Power-On Reset to Zero-Scale
        2. 8.3.3.2 Power-On Reset to Mid-Scale
        3. 8.3.3.3 Power-On Reset (POR) Levels
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
        1. 8.4.1.1 DAC Power-Down Commands
      2. 8.4.2 Gain Function
      3. 8.4.3 Software Reset Function
      4. 8.4.4 Internal Reference Enable Register
        1. 8.4.4.1 Enabling Internal Reference
        2. 8.4.4.2 Disabling Internal Reference
      5. 8.4.5 CLR Functionality
      6. 8.4.6 LDAC Functionality
    5. 8.5 Programming
      1. 8.5.1 SYNC Interrupt
      2. 8.5.2 DAC Register Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DAC Internal Reference
        1. 9.1.1.1 Supply Voltage
        2. 9.1.1.2 Temperature Drift
        3. 9.1.1.3 Noise Performance
        4. 9.1.1.4 Load Regulation
          1. 9.1.1.4.1 Long-Term Stability
        5. 9.1.1.5 Thermal Hysteresis
      2. 9.1.2 DAC Noise Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Combined Voltage and Current Analog Output Module Using the XTR300
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Up to ±15-V Bipolar Output Using the DAC8562-Q1
    3. 9.3 System Examples
      1. 9.3.1 MSP430 Microprocessor Interfacing
      2. 9.3.2 TMS320 McBSP Microprocessor Interfacing
      3. 9.3.3 OMAP-L1x Processor Interfacing
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified with the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Relative Accuracy:
    • DAC756x (12-Bit): 0.3 LSB INL
    • DAC816x (14-Bit): 1 LSB INL
    • DAC856x (16-Bit): 4 LSB INL
  • Glitch Impulse: 0.1 nV-s
  • Bidirectional Reference: Input or 2.5-V Output
    • Output Disabled by Default
    • ±5-mV Initial Accuracy (Max)
    • 4-ppm/°C Temperature Drift (Typ)
    • 10-ppm/°C Temperature Drift (Max)
    • 20-mA Sink and Source Capability
  • Power-On Reset to Zero Scale or Mid-Scale
  • Low-Power: 4 mW (Typ, 5-V AVDD, Including Internal Reference Current)
  • Wide Power-Supply Range: 2.7 V to 5.5 V
  • 50-MHz SPI With Schmitt-Triggered Inputs
  • LDAC and CLR Functions
  • Output Buffer With Rail-to-Rail Operation
  • Package: VSSOP-10

2 Applications

  • Portable Instrumentation
  • PLC Analog Output Module
  • Closed-Loop Servo Control
  • Voltage Controlled Oscillator Tuning
  • Data Acquisition Systems
  • Programmable Gain and Offset Adjustment

3 Description

The DAC756x-Q1, DAC816x-Q1, and DAC856x-Q1 (DACxx6x-Q1) devices are low-power, voltage-output, dual-channel, 12-, 14-, and 16-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the VREFIN/VREFOUT pin.

These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile three-wire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACxx62-Q1 devices incorporate a power-on-reset circuit that ensures the DAC output powers up and remains at zero scale until a valid code is written to the device, whereas the DACxx63-Q1 devices similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 550 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment.

The DACxx62-Q1 devices are drop-in and function-compatible with each device in this family, as are the DACxx63-Q1 devices. The entire family is available in a 10-pin VSSOP-10 (DGS) package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC7562-Q1 VSSOP (10) 3.00 mm × 3.00 mm
DAC7563-Q1
DAC8162-Q1
DAC8163-Q1
DAC8562-Q1
DAC8563-Q1
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

DAC7562-Q1 DAC7563-Q1 DAC8162-Q1 DAC8163-Q1 DAC8562-Q1 DAC8563-Q1 fbd_las950.gif