SNLS432C October   2012  – December 2015 DS125MB203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics - Serial Management Bus Interface
    7. 7.7 Timing Requirements - Serial Bus Interface
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 SMBUS Master Mode
    6. 8.6 Register Maps
      1. 8.6.1 System Management Bus (SMBus) and Configuration Registers
        1. 8.6.1.1 Transfer Of Data Through the SMBus
        2. 8.6.1.2 SMBus Transactions
        3. 8.6.1.3 Writing a Register
        4. 8.6.1.4 Reading a Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Recommendations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 12.5-Gbps Dual Lane 2:1 Mux, 1:2 Switch or Fanout
  • Low 390-mW Total Power (Typical)
  • Advanced Signal Conditioning Features:
    • Receive Equalization up to 30 dB at 6.25 GHz
    • Transmit De-Emphasis up to –12 dB
    • Transmit Output-Voltage Control: 600 mV to 1300 mV
  • Programmable Through Pin Selection, EEPROM or SMBus Interface
  • Selectable 2.5-V or 3.3-V Supply Voltage
  • –40°C to +85°C Operating Temperature Range

2 Applications

  • 10GE, 10G-KR
  • PCIe Gen-1/2/3
  • SAS2/SATA3 (Up to 6 Gbps)
  • XAUI, RXAUI

Simplified Functional Block Diagram

DS125MB203 MB203_simplified_schematic.gif

3 Description

The DS125MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 12.5 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 30-inch FR-4 or 8-m cable (AWG-24) at 12.5 Gbps. This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and de-emphasis of up to 12 dB.

The DS125MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen-3 mode, the DS125MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS125MB203 WQFN (54) 10.00 mm × 5.50 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

DS125MB203 MBapplication.gif