JAJSHP1E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | 0 | 0 | TEST PATTERN EN | RESET |
W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | R/W-0h | W-0h |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | 0 | W | 0h | Must write 0 |
1 | TEST PATTERN EN | R/W | 0h | This bit enables test pattern selection for the digital outputs. 0 = Normal output 1 = Test pattern output enabled |
0 | RESET | W | 0h | This bit applies a software reset. This bit resets all internal registers to the default values and self-clears to 0. |