JAJSCY0A January   2017  – August 2017 ADS7039-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Input
      3. 8.3.3 ADC Transfer Function
      4. 8.3.4 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration
        1. 8.4.1.1 Offset Calibration on Power-Up
        2. 8.4.1.2 Offset Calibration During Normal Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Low Distortion Charge Kickback Filter Design
        2. 9.2.2.2 Input Amplifier Selection
        3. 9.2.2.3 Reference Circuit
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Estimating Digital Power Consumption
    3. 10.3 Optimizing Power Consumed by the Device
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Description

Overview

The ADS7039-Q1 is an ultra-low-power, miniature analog-to-digital converter (ADC) that supports a wide analog input range. The analog input range for the device is defined by the AVDD supply voltage. The device samples the input voltage across the AINP and AINM pins on the CS falling edge and starts the conversion. The clock provided on the SCLK pin is used for conversion and data transfer. During conversions, both the AINP and AINM pins are disconnected from the sampling circuit. After the conversion completes, the sampling capacitors are reconnected across the AINP and AINM pins and the ADS7039-Q1 enters acquisition phase.

The device has an internal offset calibration. The offset calibration can be initiated by the user either on power-up or during normal operation; see the Offset Calibration section for more details.

The device also provides a simple serial interface to the host controller and operates over a wide range of digital power supplies. The ADS7039-Q1 requires only a 28-MHz SCLK for supporting a throughput of 2 MSPS. The digital interface also complies with the JESD8-7A (normal range) standard. The Functional Block Diagram section provides a block diagram of the device.

Functional Block Diagram

ADS7039-Q1 fbd_bas608.gif

Feature Description

Reference

The device uses the analog supply voltage (AVDD) as a reference, as shown in Figure 31. The AVDD pin is recommended to be decoupled with a 3.3-µF, low equivalent series resistance (ESR) ceramic capacitor.. The AVDD pin functions as a switched capacitor load to the source powering AVDD. The decoupling capacitor provides the instantaneous charge required by the internal circuit and helps in maintaining a stable dc voltage on the AVDD pin. The AVDD pin is recommended to be powered with a low output impedance and low-noise regulator (such as the TPS73230).

ADS7039-Q1 ref_bas608.gif Figure 31. Reference for the Device

Analog Input

The device supports single-ended analog inputs. The ADC samples the difference between AINP and AINM and converts for this voltage. The device is capable of accepting a signal from –100 mV to 100 mV on the AINM input and is useful in systems where the sensor or signal-conditioning block is far from the ADC. In such a scenario, there can be a difference between the ground potential of the sensor or signal conditioner and the ADC ground. In such cases, use separate wires to connect the ground of the sensor or signal conditioner to the AINM pin. The AINP input is capable of accepting signals from 0 V to AVDD. Figure 32 represents the equivalent analog input circuits for the sampling stage. The device has a low-pass filter followed by the sampling switch and sampling capacitor. The sampling switch is represented by an RS (typically 50 Ω) resistor in series with an ideal switch and CS (typically 15 pF) is the sampling capacitor. The ESD diodes are connected from both analog inputs to AVDD and ground.

ADS7039-Q1 ain_bas608.gif Figure 32. Equivalent Input Circuit for the Sampling Stage

The analog input full-scale range (FSR) is equal to the reference voltage of the ADC. The reference voltage for the device is equal to the analog supply voltage (AVDD). Thus, the device FSR can be determined by Equation 1:

Equation 1. FSR = VREF = AVDD

ADC Transfer Function

The device output is in straight binary format. The device resolution for a single-ended input can be computed by Equation 2:

Equation 2. 1 LSB = VREF / 2N

where

  • VREF = AVDD and
  • N = 10

Figure 33 and Table 1 show the ideal transfer characteristics for the device.

ADS7039-Q1 ai_transfer_chara_bas608.gif Figure 33. Ideal Transfer Characteristics

Table 1. Transfer Characteristics

INPUT VOLTAGE (AINP – AINM) CODE DESCRIPTION IDEAL OUTPUT CODE (HEX)
≤1 LSB NFSC Negative full-scale code 000
1 LSB to 2 LSBs NFSC + 1 001
(VREF / 2) to (VREF / 2) + 1 LSB MC Mid code 200
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs MC + 1 201
≥ VREF – 1 LSB PFSC Positive full-scale code 3FF

Serial Interface

The device supports a simple, SPI-compatible interface to the external host. The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The SDO pin outputs the ADC conversion results. Figure 34 shows a detailed timing diagram for the serial interface. A minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The device uses the clock provided on the SCLK pin for conversion and data transfer. The conversion result is available on the SDO pin with the first two bits set to 0, followed by 10 bits of the conversion result. The first zero is launched on the SDO pin on the CS falling edge. Subsequent bits (starting with another 0 followed by the conversion result) are launched on the SDO pin on subsequent SCLK falling edges. The SDO output remains low after 12 SCLKs. A CS rising edge ends the frame and brings the serial data bus to tri-state. For acquisition of the next sample, a minimum time of tACQ must be provided after the conversion of the current sample is completed. For details on timing specifications, see the Timing Requirements table.

The device initiates an offset calibration on the first CS falling edge after power-up and the SDO output remains low during the first serial transfer frame after power-up. For further details, see the Offset Calibration section.

ADS7039-Q1 ai_timing_sbas788.gif Figure 34. Serial Interface Timing Diagram

Device Functional Modes

Offset Calibration

The ADS7039-Q1 includes a feature to calibrate the device internal offset. During offset calibration, the analog input pins (AINP and AINM) are disconnected from the sampling stage. The device includes an internal offset calibration register (OCR) that stores the offset calibration result. The OCR is an internal register and cannot be accessed by the user through the serial interface. The OCR is reset to zero on power-up. Therefore, it is recommended to calibrate the offset on power-up in order to bring the offset error within the specified limits. If the operating temperature or analog supply voltage reflect a significant change, the offset can be recalibrated during normal operation. Figure 35 shows the offset calibration process.

ADS7039-Q1 dev_offset_sd_bas608.gif
See the Timing Requirements section for timing specifications.
See the Offset Calibration During Normal Operation section for details.
See the Offset Calibration on Power-Up section for details.
The power recycle on the AVDD supply is required to reset the offset calibration and to bring the device to a power-up state.
Figure 35. Offset Calibration

Offset Calibration on Power-Up

The device initiates offset calibration on the first CS falling edge after power-up and calibration completes if the CS pin remains low for at least 16 SCLK falling edges after the first CS falling edge. The SDO output remains low during calibration. The minimum acquisition time must be provided after calibration for acquiring the first sample. If the device is not provided with at least 16 SCLKs during the first serial transfer frame after power-up, the OCR is not updated. Table 2 provides the timing parameters for offset calibration on power-up.

For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The conversion result adjusted with the value stored in OCR is provided by the device on the SDO output. Figure 36 shows the timing diagram for offset calibration on power-up.

Table 2. Offset Calibration on Power-Up

MIN TYP MAX UNIT
fCLK-CAL SCLK frequency for calibration 14 MHz
tPOWERUP-CAL Calibration time at power-up 15 × tSCLK ns
tACQ Acquisition time 120 ns
tPH_CS CS high time tACQ ns
tSU_CSCK Setup time: CS falling to SCLK falling 12 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns
ADS7039-Q1 cal_16clk_pwr_up_sbas788.gif Figure 36. Offset Calibration on Power-Up Timing Diagram

Offset Calibration During Normal Operation

Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in one serial transfer frame. During the first 12 SCLKs, the device converts the sample acquired on the CS falling edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 12th SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32 SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset calibration during normal operation.

For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output. Figure 37 shows the timing diagram for offset calibration during normal operation.

Table 3. Offset Calibration During Normal Operation

MIN TYP MAX UNIT
fCLK-CAL SCLK frequency for calibration 14 MHz
tCAL Calibration time during normal operation 15 × tSCLK ns
tACQ Acquisition time 120 ns
tPH_CS CS high time tACQ ns
tSU_CSCK Setup time: CS falling to SCLK falling 12 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns
ADS7039-Q1 cal_32clk_sbas788.gif Figure 37. Offset Calibration During Normal Operation Timing Diagram