JAJSEC1C November 2019 – July 2020 ADS8686S
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
DEVICE CONFIGURATION | |||||
tD_ CSCNV | Delay time: CS rising edge to CONVST rising edge | 50 | ns | ||
tSU_CHXCNV | Setup time: CHSELx to CONVST rising edge | 50 | ns | ||
tHT_BSYCHX | Hold time: BUSY falling edge to CHSELx change | 20 | ns | ||
tPWRUP | Power supplies settled to RESET rising edge | 1 | ms | ||
tDEV_WRITE | Partial reset: RESET rising edge to first falling edge of CS | 50 | ns | ||
Full reset: RESET rising edge to first falling edge of CS | 240 | µs | |||
tSU_ RST | Partial reset: setup time HW mode configuration inputs to RESET rising edge | 10 | ns | ||
Full reset: setup time HW mode configuration inputs to RESET rising edge | 50 | µs | |||
tHT_ RST | Partial reset: hold time RESET rising edge to HW mode configuration inputs | 10 | ns | ||
Full reset: Hold time RESET rising edge to HW mode configuration inputs | 240 | µs | |||
CONVST CONTROL | |||||
tACQ | Acquisition time: BUSY falling edge to rising edge of trailing CONVST | 480 | ns | ||
tPH_CNV | CONVST pulse high time | 50 | ns | ||
tPL_CNV | CONVST pulse low time | 50 | ns | ||
tDEV_STRTUP | Partial reset setup time: RESET rising edge to first rising edge of CONVST | 50 | ns | ||
Full reset setup time: RESET rising edge to first rising edge of CONVST | 15 | ms | |||
tPL_ RST | Partial reset | 40 | 500 | ns | |
Full reset | 1.2 | µs | |||
DATA READ | |||||
tSU_BSY CS | Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion | 20 | ns | ||
tDZ_ CSCNV | Delay between CS rising edge to CONVST rising edge, end of data read operation after conversion | 50 | ns | ||
PARALLEL AND BYTE DATA READ | |||||
tSU_ CSRD | Setup time: CS falling edge to RD falling edge | 10 | ns | ||
tHT_ RDCS | Hold time: RD rising edge to CS rising edge | 10 | ns | ||
tPH_ RD | RD high time | 10 | ns | ||
tPL_ RD | RD low time | 30 | ns | ||
SERIAL DATA READ | |||||
tSCLK | SCLK time period, 1.71 V ≤ DVDD ≤ 2.3 V | 50 | ns | ||
SCLK time period, 2.3 V < DVDD ≤ 3 V | 25 | ns | |||
SCLK time period, DVDD > 3 V | 20 | ns | |||
tPH_SCLK | SCLK high time | 0.45 | 0.55 | tSCLK | |
tPL_SCLK | SCLK low time | 0.45 | 0.55 | tSCLK | |
tSU_ CSCK | Setup time:
CS falling edge to SCLK falling edge DVDD > 3V | 10.5 | ns | ||
Setup time:
CS falling edge to SCLK falling edge 2.3 V < DVDD ≤ 3 V | 13.5 | ns | |||
Setup time:
CS falling edge to SCLK falling edge 1.71 V ≤ DVDD ≤ 2.3 V | 20 | ns | |||
tHT_CK CS | Hold time: SCLK to CS rising time | 10 | ns | ||
PARALLEL AND BYTE DATA WRITE | |||||
tSU_ CSWR | Setup time: CS falling edge to WR falling edge | 10 | ns | ||
tHT_ WRCS | Hold time: WR rising edge to CS rising edge | 10 | ns | ||
tPH_ WR | WR high time | 20 | ns | ||
tPL_ WR | WR low time | 30 | ns | ||
tSU_DIN WR | Setup time: DIN change to WR rising edge | 30 | ns | ||
tHT_ WRDIN | Hold time: WR rising edge to DIN change | 10 | ns | ||
tDZ_CONFIG | Device configuration time: WR rising edge to CONVST rising edge | 20 | ns | ||
SERIAL DATA WRITE | |||||
tSU_DINCK | Setup time: DIN to SCLK falling edge | 10 | ns | ||
tHT_CKDIN | Hold time: SCLK falling edge to DIN change | 8 | ns |