JAJSEF2D
June 2013 – December 2021
DAC7760
,
DAC8760
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Electrical Characteristics: AC
7.7
Timing Requirements: Write Mode
7.8
Timing Requirements: Readback Mode
7.9
Timing Diagrams
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
DAC Architecture
8.3.2
Voltage Output Stage
8.3.3
Current Output Stage
8.3.4
Internal Reference
8.3.5
Digital Power Supply
8.3.6
DAC Clear
8.3.7
Power-On Reset
8.3.8
Alarm Detection
8.3.9
Watchdog Timer
8.3.10
Frame Error Checking
8.3.11
User Calibration
8.3.12
Programmable Slew Rate
8.4
Device Functional Modes
8.4.1
Setting Voltage and Current Output Ranges
8.4.2
Boost Configuration for IOUT
8.4.3
Filtering the Current Output (only on the VQFN package)
8.4.4
HART Interface
8.4.4.1
For 4-mA to 20-mA Mode
8.4.4.2
For All Current Output Modes
8.5
Programming
8.5.1
Serial Peripheral Interface (SPI)
8.5.1.1
SPI Shift Register
8.5.1.2
Write Operation
8.5.1.3
Read Operation
8.5.1.4
Stand-Alone Operation
8.5.1.5
Multiple Devices on the Bus
8.6
Register Maps
8.6.1
DACx760 Command and Register Map
8.6.1.1
DACx760 Register Descriptions
8.6.1.1.1
Control Register
8.6.1.1.2
Configuration Register
8.6.1.1.3
DAC Registers
8.6.1.1.4
Reset Register
8.6.1.1.5
Status Register
9
Application and Implementation
9.1
Application Information
9.1.1
Controlling the VOUT and IOUT Pins
9.1.1.1
VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
9.1.1.2
VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
9.1.1.3
VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
9.1.2
Implementing HART in All Current Output Modes
9.1.2.1
Using CAP2 Pin on VQFN Package
9.1.2.2
Using the ISET-R Pin
9.1.3
Short-Circuit Current Limiting
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Thermal Considerations
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PWP|24
MPDS372A
RHA|40
MPQF135D
サーマルパッド・メカニカル・データ
PWP|24
PPTD264C
RHA|40
QFND114P
発注情報
jajsef2d_oa
jajsef2d_pm
7.9
Timing Diagrams
Figure 7-1
Write Mode Timing
Figure 7-2
Readback Mode Timing