JAJSEF2D June   2013  – December 2021 DAC7760 , DAC8760

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-On Reset
      8. 8.3.8  Alarm Detection
      9. 8.3.9  Watchdog Timer
      10. 8.3.10 Frame Error Checking
      11. 8.3.11 User Calibration
      12. 8.3.12 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Command and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.2.1 Using CAP2 Pin on VQFN Package

The first method of implementing HART is to couple the signal through the CAP2 pin, as conceptualized in Figure 9-3. Note that this pin is only available in the 40-pin VQFN package.

GUID-57F6B5D6-28E5-4892-BB6D-1B3EE52716B5-low.gifFigure 9-3 Implementing HART on IOUT Using the CAP2 Pin

In Figure 9-3, R3 is nominally 40 Ω, and R2 is dependent on the current output range (set by the RANGE bits) as described below:

  • 4-mA to 20-mA range: R2 = 2.4 kΩ typical
  • 0-mA to 20-mA range: R2 = 3 kΩ typical
  • 0-mA to 24-mA range: R2 = 3.6 kΩ typical

The purpose of the 12.5-kΩ resistor is to create a filter when CAP1 and CAP2 are used.

To insert the external HART signal on the CAP2 pin, an external ac-coupling capacitor is typically connected to CAP2. The high-pass filter 3-dB frequency would be determined by the resistive impedance looking into CAP2 (R2 + 12.5 kΩ) and the coupling capacitor value. The 3-dB frequency would be 1 /(2 × π × [R2 + 12.5 kΩ] × [Coupling Cap Value]).

After the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of amplifier A2 and would therefore be seen across the 40-Ω resistor. To generate a 1-mA signal on the output would therefore require a 40-mV peak-to-peak signal on CAP2. Because most HART modems do not output a 40-mV signal, a capacitive divider is used in the above circuit to attenuate the FSK signal from the modem. In the above circuit, the high-pass cutoff frequency would be 1 / (2 × π × [R2+12.5 kΩ] × [C1 + C2]). There is one disadvantage of this approach: if the AVDD supply was not clean, any ripple on it could couple into the part.