POWER-UP TIMING |
T2.1.1 |
Post Power-Up Stabilization time prior to MDC preamble for register accesses(1) |
MDIO is pulled high for 32-bit serial management initialization |
167 |
|
|
ms |
X1 Clock must be stable for a min. of 167 ms at power up. |
T2.1.2 |
Hardware Configuration Latch-in Time from power up(1) |
Hardware Configuration Pins are described in the Section 4 section. |
167 |
|
|
ms |
X1 Clock must be stable for a min. of 167 ms at power up. |
T2.1.3 |
Hardware Configuration pins transition to output drivers |
|
|
50 |
|
ns |
RESET TIMING |
T2.2.1 |
Post RESET Stabilization time prior to MDC preamble for register accesses(2) |
MDIO is pulled high for 32-bit serial management initialization |
|
3 |
|
µs |
T2.2.2 |
Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard)(2) |
Hardware Configuration Pins are described in the Section 4 section |
|
3 |
|
µs |
T2.2.3 |
Hardware Configuration pins transition to output drivers |
|
|
50 |
|
ns |
T2.2.4 |
RESET pulse width |
X1 Clock must be stable for at min. of 1us during RESET pulse low time. |
1 |
|
|
µs |
MII SERIAL MANAGEMENT TIMING |
T2.3.1 |
MDC to MDIO (Output) Delay Time |
|
0 |
|
30 |
ns |
T2.3.2 |
MDIO (Input) to MDC Setup Time |
|
10 |
|
|
ns |
T2.3.3 |
MDIO (Input) to MDC Hold Time |
|
10 |
|
|
ns |
T2.3.4 |
MDC Frequency |
|
|
2.5 |
25 |
MHz |
100 Mb/s MII TRANSMIT TIMING |
T2.4.1 |
TX_CLK High/Low Time |
100 Mb/s Normal mode |
16 |
20 |
24 |
ns |
T2.4.2 |
TXD[3:0], TX_EN Data Setup to TX_CLK |
100 Mb/s Normal mode |
10 |
|
|
ns |
T2.4.3 |
TXD[3:0], TX_EN Data Hold from TX_CLK |
100 Mb/s Normal mode |
0 |
|
|
ns |
100 Mb/s MII RECEIVE TIMING |
T2.5.1 |
RX_CLK High/Low Time(3) |
100 Mb/s Normal mode |
16 |
20 |
24 |
ns |
T2.5.2 |
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay |
100 Mb/s Normal mode |
10 |
|
30 |
ns |
100BASE-TX MII TRANSMIT PACKET LATENCY TIMING |
T2.6.1 |
TX_CLK to PMD Output Pair Latency(4) |
100BASE-TX mode |
|
6 |
|
bits |
100BASE-TX TRANSMIT PACKET DEASSERTION TIMING |
T2.7.1 |
TX_CLK to PMD Output Pair Deassertion(5) |
100BASE-TX mode |
|
5 |
|
bits |
100BASE-TX TRANSMIT TIMING (tR/F and Jitter) |
T2.8.1 |
100 Mb/s PMD Output Pair tR and tF(7) |
|
3 |
4 |
5 |
ns |
100 Mb/s tR and tF Mismatch(6)(7) |
|
|
|
500 |
ps |
T2.8.2 |
100 Mb/s PMD Output Pair Transmit Jitter |
|
|
|
1.4 |
ns |
100BASE-TX RECEIVE PACKET LATENCY TIMING(10) |
T2.9.1 |
Carrier Sense ON Delay(8) |
100 Mb/s Normal mode(9) |
|
20 |
|
bits |
T2.9.2 |
Receive Data Latency |
100 Mb/s Normal mode(9) |
|
24 |
|
bits |
100BASE-TX RECEIVE PACKET DEASSERTION TIMING |
T2.10.1 |
Carrier Sense OFF Delay(11) |
100 Mb/s Normal mode(9) |
|
24 |
|
bits |
10 Mb/s MII TRANSMIT TIMING(12) |
T2.11.1 |
TX_CLK High/Low Time |
10 Mb/s MII mode |
190 |
200 |
210 |
ns |
T2.11.2 |
TXD[3:0], TX_EN Data Setup to TX_CLK fall |
10 Mb/s MII mode |
25 |
|
|
ns |
T2.11.3 |
TXD[3:0], TX_EN Data Hold from TX_CLK rise |
10 Mb/s MII mode |
0 |
|
|
ns |
10 Mb/s MII RECEIVE TIMING |
T2.12.1 |
RX_CLK High/Low Time(13) |
|
160 |
200 |
240 |
ns |
T2.12.2 |
RX_CLK TO RXD[3:0}, RX_DV Delay |
10 Mb/s MII mode |
100 |
|
|
ns |
T2.12.3 |
RX_CLK rising edge delay from RXD[3:0], RX_DV Valid |
10 Mb/s MII mode |
100 |
|
|
ns |
10 Mb/s SERIAL MODE (SNI) TRANSMIT TIMING |
T2.13.1 |
TX_CLK High Time |
10 Mb/s Serial mode (SNI) |
20 |
25 |
30 |
ns |
T2.13.2 |
TX_CLK Low Time |
10 Mb/s Serial mode (SNI) |
70 |
75 |
80 |
ns |
T2.13.3 |
TXD_0, TX_EN Data Setup to TX_CLK rise |
10 Mb/s Serial mode (SNI) |
25 |
|
|
ns |
T2.13.4 |
TXD_0, TX_EN Data Hold from TX_CLK rise |
10 Mb/s Serial mode (SNI) |
0 |
|
|
ns |
10 Mb/s SERIAL MODE (SNI) RECEIVE TIMING |
T2.14.1 |
RX_CLK High/Low Time(14) |
|
35 |
50 |
65 |
ns |
T2.14.2 |
RX_CLK fall to RXD_0, RX_DV Delay |
10 Mb/s Serial mode (SNI) |
–10 |
|
10 |
ns |
10BASE-T TRANSMIT TIMING (START OF PACKET) |
T2.15.1 |
Transmit Output Delay from the |
10 Mb/s MII mode(15) |
|
3.5 |
|
bits |
Falling Edge of TX_CLK |
T2.15.2 |
Transmit Output Delay from the |
10 Mb/s Serial mode (SNI)(15) |
|
3.5 |
|
bits |
Rising Edge of TX_CLK |
10BASE-T TRANSMIT TIMING (END OF PACKET) |
T2.16.1 |
End of Packet High Time |
|
250 |
300 |
|
ns |
(with '0' ending bit) |
T2.16.2 |
End of Packet High Time |
|
250 |
300 |
|
ns |
(with '1' ending bit) |
10BASE-T RECEIVE TIMING (START OF PACKET)(17) |
T2.17.1 |
Carrier Sense Turnon Delay (PMD Input Pair to CRS) |
|
|
630 |
1000 |
ns |
T2.17.2 |
RX_DV Latency(16) |
|
|
10 |
|
bits |
T2.17.3 |
Receive Data Latency |
Measurement shown from SFD |
|
8 |
|
bits |
10BASE-T RECEIVE TIMING (END OF PACKET) |
T2.18.1 |
Carrier Sense Turn Off Delay |
|
|
|
1 |
µs |
10 Mb/s HEARTBEAT TIMING |
T2.19.1 |
CD Heartbeat Delay |
10 Mb/s half-duplex mode |
|
1200 |
|
ns |
T2.19.2 |
CD Heartbeat Duration |
10 Mb/s half-duplex mode |
|
1000 |
|
ns |
10 Mb/s JABBER TIMING |
T2.20.1 |
Jabber Activation Time |
|
|
85 |
|
ms |
T2.20.2 |
Jabber Deactivation Time |
|
|
500 |
|
ms |
10BASE-T NORMAL LINK PULSE TIMING(18) |
T2.21.1 |
Pulse Width |
|
|
100 |
|
ns |
T2.21.2 |
Pulse Period |
|
|
16 |
|
ms |
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING(18) |
T2.22.1 |
Clock, Data Pulse Width |
|
|
100 |
|
ns |
T2.22.2 |
Clock Pulse to Clock Pulse |
|
|
125 |
|
µs |
Period |
T2.22.3 |
Clock Pulse to Data Pulse |
Data = 1 |
|
62 |
|
µs |
Period |
T2.22.4 |
Burst Width |
|
|
2 |
|
ms |
T2.22.5 |
FLP Burst to FLP Burst Period |
|
|
16 |
|
ms |
100BASE-TX SIGNAL DETECT TIMING(19) |
T2.23.1 |
SD Internal Turnon Time |
|
|
|
1 |
ms |
T2.23.2 |
SD Internal Turnoff Time |
|
|
|
350 |
µs |
100 Mb/s INTERNAL LOOPBACK TIMING |
T2.24.1 |
TX_EN to RX_DV Loopback(21) |
100 Mb/s internal loopback mode(20) |
|
|
240 |
ns |
10 Mb/s INTERNAL LOOPBACK TIMING |
T2.25.1 |
TX_EN to RX_DV Loopback(21) |
10 Mb/s internal loopback mode |
|
|
2 |
µs |
RMII TRANSMIT TIMING |
T2.26.1 |
X1 Clock Period |
50 MHz Reference Clock |
|
20 |
|
ns |
T2.26.2 |
TXD[1:0], TX_EN, Data Setup to X1 rising |
|
4 |
|
|
ns |
T2.26.3 |
TXD[1:0], TX_EN, Data Hold from X1 rising |
|
2 |
|
|
ns |
T2.26.4 |
X1 Clock to PMD Output Pair Latency |
From X1 Rising edge to first bit of symbol |
|
17 |
|
bits |
RMII RECEIVE TIMING |
T2.27.1 |
X1 Clock Period |
50 MHz Reference Clock |
|
20 |
|
ns |
T2.27.2 |
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising(22)(23)(24) |
|
2 |
|
14 |
ns |
T2.27.3 |
CRS ON delay (100Mb) |
From JK symbol on PMD Receive Pair to initial assertion of CRS_DV |
|
18.5 |
|
bits |
T2.27.4 |
CRS OFF delay (100Mb) |
From TR symbol on PMD Receive Pair to initial deassertion of CRS_DV |
|
27 |
|
bits |
T2.27.5 |
RXD[1:0] and RX_ER latency (100Mb) |
From symbol on Receive Pair. Elasticity buffer set to default value (01) |
|
38 |
|
bits |
ISOLATION TIMING |
T2.28.1 |
From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode |
|
|
|
100 |
µs |
T2.28.2 |
From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode |
|
|
|
500 |
µs |
25 MHz_OUT TIMING |
T2.29.1 |
25 MHz_OUT High/Low Time(25) |
MII mode |
|
20 |
|
ns |
RMII mode |
|
10 |
|
ns |
T2.29.2 |
25 MHz_OUT propagation delay(25) |
Relative to X1 |
|
|
8 |
ns |
100 Mb/s X1 TO TX_CLK TIMING |
T2.30.1 |
X1 to TX_CLK delay(26) |
100 Mb/s Normal mode |
0 |
|
5 |
ns |