JAJSFR7F June 2016 – May 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718
PRODUCTION DATA.
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CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.
Table 5-47 and Table 5-48 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-23, Figure 5-24, Figure 5-25, Figure 5-26, Figure 5-27 and Figure 5-28).
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
F12 | tsu(dV-clkH) | Setup time, read gpmc_ad[15:0] valid before gpmc_clk high | 3 | ns | |
F13 | th(clkH-dV) | Hold time, read gpmc_ad[15:0] valid after gpmc_clk high | 1.1 | ns | |
F21 | tsu(waitV-clkH) | Setup time, gpmc_wait[1:0] valid before gpmc_clk high | 2.5 | ns | |
F22 | th(clkH-waitV) | Hold Time, gpmc_wait[1:0] valid after gpmc_clk high | 1.3 | ns |
NOTE
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the Device TRM.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
F0 | tc(clk) | Cycle time, output clock gpmc_clk period | 11.3 | ns | |
F2 | td(clkH-nCSV) | Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition | F-1.7 (7) | F+4.3 (7) | ns |
F3 | td(clkH-nCSIV) | Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid | E-1.7 (6) | E+4.2 (6) | ns |
F4 | td(ADDV-clk) | Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge | B-1.8 (3) | B+4.3 (3) | ns |
F5 | td(clkH-ADDIV) | Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid | -1.8 | ns | |
F6 | td(nBEV-clk) | Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge | B-4.3(3) | B+1.5(3) | ns |
F7 | td(clkH-nBEIV) | Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid | D-1.5(5) | D+4.3(5) | ns |
F8 | td(clkH-nADV) | Delay time, gpmc_clk rising edge to gpmc_advn_ale transition | G-1.3 (8) | G+4.2 (8) | ns |
F9 | td(clkH-nADVIV) | Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid | D-1.3 (5) | G+4.2 (5) | ns |
F10 | td(clkH-nOE) | Delay time, gpmc_clk rising edge to gpmc_oen_ren transition | H-1.0 (9) | H+3.2 (9) | ns |
F11 | td(clkH-nOEIV) | Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid | E-1.0 (6) | E+3.2 (6) | ns |
F14 | td(clkH-nWE) | Delay time, gpmc_clk rising edge to gpmc_wen transition | I-0.9 (10) | I+4.2 (10) | ns |
F15 | td(clkH-Data) | Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition | J-2.1 (11) | J+4.6 (11) | ns |
F17 | td(clkH-nBE) | Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition | J-1.5 (11) | J+4.3 (11) | ns |
F18 | tw(nCSV) | Pulse duration, gpmc_cs[7:0] low | A (2) | ns | |
F19 | tw(nBEV) | Pulse duration, gpmc_ben[1:0] low | C (4) | ns | |
F20 | tw(nADVV) | Pulse duration, gpmc_advn_ale low | K (12) | ns | |
F23 | td(CLK-GPIO) | Delay time, gpmc_clk transition to gpio6_16 transition | 0.5 | 7.5 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
F12 | tsu(dV-clkH) | Setup time, read gpmc_ad[15:0] valid before gpmc_clk high | 2.5 | ns | |
F13 | th(clkH-dV) | Hold time, read gpmc_ad[15:0] valid after gpmc_clk high | 1.9 | ns | |
F21 | tsu(waitV-clkH) | Setup time, gpmc_wait[1:0] valid before gpmc_clk high | 2.5 | ns | |
F22 | th(clkH-waitV) | Hold Time, gpmc_wait[1:0] valid after gpmc_clk high | 1.9 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
F0 | tc(clk) | Cycle time, output clock gpmc_clk period (13) | 15.04 | ns | |
F2 | td(clkH-nCSV) | Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition | F+0.6 (7) | F+7.0 (7) | ns |
F3 | td(clkH-nCSIV) | Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid | E+0.6 (6) | E+7.0 (6) | ns |
F4 | td(ADDV-clk) | Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge | B-0.7 (3) | B+7.0 (3) | ns |
F5 | td(clkH-ADDIV) | Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid | -0.7 | ns | |
F6 | td(nBEV-clk) | Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge | B-7.0 | B+0.4 | ns |
F7 | td(clkH-nBEIV) | Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid | D-0.4 | D+7.0 | ns |
F8 | td(clkH-nADV) | Delay time, gpmc_clk rising edge to gpmc_advn_ale transition | G+0.7 (8) | G+6.1 (8) | ns |
F9 | td(clkH-nADVIV) | Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid | D+0.7 (5) | D+6.1 (5) | ns |
F10 | td(clkH-nOE) | Delay time, gpmc_clk rising edge to gpmc_oen_ren transition | H+0.7 (9) | H+5.1 (9) | ns |
F11 | td(clkH-nOEIV) | Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid | E+0.7 (6) | E+5.1 (6) | ns |
F14 | td(clkH-nWE) | Delay time, gpmc_clk rising edge to gpmc_wen transition | I+0.7 (10) | I+6.1 (10) | ns |
F15 | td(clkH-Data) | Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition | J-0.4 (11) | J+4.9 (11) | ns |
F17 | td(clkH-nBE) | Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition | J-0.4 (11) | J+4.9 (11) | ns |
F18 | tw(nCSV) | Pulse duration, gpmc_cs[7:0] low | A (2) | ns | |
F19 | tw(nBEV) | Pulse duration, gpmc_ben[1:0] low | C (4) | ns | |
F20 | tw(nADVV) | Pulse duration, gpmc_advn_ale low | K (12) | ns | |
F23 | td(CLK-GPIO) | Delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14) | 0.5 | 7.5 | ns |