JAJSD42B February 2017 – December 2017 DRV8320 , DRV8320R , DRV8323 , DRV8323R
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
POWER SUPPLIES (DVDD, VCP, VM) | ||||||||
IVM | VM operating supply current | VVM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 10.5 | 14 | mA | |||
IVMQ | VM sleep mode supply current | ENABLE = 0 V, VVM = 24 V, TA = 25°C | 12 | 20 | µA | |||
ENABLE = 0 V, VVM = 24 V, TA = 125°C(1) | 50 | |||||||
tRST(1) | Reset pulse time | ENABLE = 0 V period to reset faults | 8 | 40 | µs | |||
tWAKE | Turnon time | VVM > VUVLO, ENABLE = 3.3 V to outputs ready | 1 | ms | ||||
tSLEEP | Turnoff time | ENABLE = 0 V to device sleep mode | 1 | ms | ||||
VDVDD | DVDD regulator voltage | IDVDD = 0 to 30 mA | 3 | 3.3 | 3.6 | V | ||
VVCP | VCP operating voltage
with respect to VM |
VVM = 13 V, IVCP = 0 to 25 mA | 8.4 | 11 | 12.5 | V | ||
VVM = 10 V, IVCP = 0 to 20 mA | 6.3 | 9 | 10 | |||||
VVM = 8 V, IVCP = 0 to 15 mA | 5.4 | 7 | 8 | |||||
VVM = 6 V, IVCP = 0 to 10 mA | 4 | 5 | 6 | |||||
LOGIC-LEVEL INPUTS (CAL, ENABLE, INHx, INLx, nSCS, SCLK, SDI) | ||||||||
VIL | Input logic low voltage | 0 | 0.8 | V | ||||
VIH | Input logic high voltage | 1.5 | 5.5 | V | ||||
VHYS | Input logic hysteresis | 100 | mV | |||||
IIL | Input logic low current | VVIN = 0 V | –5 | 5 | µA | |||
IIH | Input logic high current | VVIN = 5 V | 50 | 70 | µA | |||
RPD | Pulldown resistance | To AGND | 100 | kΩ | ||||
tPD | Propagation delay | INHx/INLx transition to GHx/GLx transition | 150 | ns | ||||
FOUR-LEVEL H/W INPUTS (GAIN, MODE) | ||||||||
VI1 | Input mode 1 voltage | Tied to AGND | 0 | V | ||||
VI2 | Input mode 2 voltage | 45 kΩ ± 5% to tied AGND | 1.2 | V | ||||
VI3 | Input mode 3 voltage | Hi-Z | 2 | V | ||||
VI4 | Input mode 4 voltage | Tied to DVDD | 3.3 | V | ||||
RPU | Pullup resistance | Internal pullup to DVDD | 50 | kΩ | ||||
RPD | Pulldown resistance | Internal pulldown to AGND | 84 | kΩ | ||||
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS) | ||||||||
VI1 | Input mode 1 voltage | Tied to AGND | 0 | V | ||||
VI2 | Input mode 2 voltage | 18 kΩ ± 5% tied to AGND | 0.5 | V | ||||
VI3 | Input mode 3 voltage | 75 kΩ ± 5% tied to AGND | 1.1 | V | ||||
VI4 | Input mode 4 voltage | Hi-Z | 1.65 | V | ||||
VI5 | Input mode 5 voltage | 75 kΩ ± 5% tied to DVDD | 2.2 | V | ||||
VI6 | Input mode 6 voltage | 18 kΩ ± 5% tied to DVDD | 2.8 | V | ||||
VI7 | Input mode 7 voltage | Tied to DVDD | 3.3 | V | ||||
RPU | Pullup resistance | Internal pullup to DVDD | 73 | kΩ | ||||
RPD | Pulldown resistance | Internal pulldown to AGND | 73 | kΩ | ||||
OPEN DRAIN OUTPUTS (nFAULT, SDO) | ||||||||
VOL | Output logic low voltage | IO = 5 mA | 0.1 | V | ||||
IOZ | Output high impedance leakage | VO = 5 V | –2 | 2 | µA | |||
GATE DRIVERS (GHx, GLx) | ||||||||
VGSH (1) | High-side gate drive voltage
with respect to SHx |
VVM = 13 V, IVCP = 0 to 25 mA | 8.4 | 11 | 12.5 | V | ||
VVM = 10 , IVCP = 0 to 20 mA | 6.3 | 9 | 10 | |||||
VVM = 8 V, IVCP = 0 to 15 mA | 5.4 | 7 | 8 | |||||
VVM = 6 V, IVCP = 0 to 10 mA | 4 | 5 | 6 | |||||
VGSL(1) | Low-side gate drive voltage
with respect to PGND |
VVM = 12 V, IVGLS = 0 to 25 mA | 9 | 11 | 12 | V | ||
VVM = 10 V, IVGLS = 0 to 20 mA | 7.5 | 9 | 10 | |||||
VVM = 8 V, IVGLS = 0 to 15 mA | 5.5 | 7 | 8 | |||||
VVM = 6 V, IVGLS = 0 to 10 mA | 4 | 5 | 6 | |||||
tDEAD | Gate drive
dead time |
SPI Device | DEAD_TIME = 00b | 50 | ns | |||
DEAD_TIME = 01b | 100 | |||||||
DEAD_TIME = 10b | 200 | |||||||
DEAD_TIME = 11b | 400 | |||||||
H/W Device | 100 | |||||||
tDRIVE | Peak current
gate drive time |
SPI Device | TDRIVE = 00b | 500 | ns | |||
TDRIVE = 01b | 1000 | |||||||
TDRIVE = 10b | 2000 | |||||||
TDRIVE = 11b | 4000 | |||||||
H/W Device | 4000 | |||||||
IDRIVEP | Peak source
gate current |
SPI Device | IDRIVEP_HS or IDRIVEP_LS = 0000b | 10 | mA | |||
IDRIVEP_HS or IDRIVEP_LS = 0001b | 30 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0010b | 60 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0011b | 80 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0100b | 120 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0101b | 140 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0110b | 170 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 0111b | 190 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1000b | 260 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1001b | 330 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1010b | 370 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1011b | 440 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1100b | 570 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1101b | 680 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1110b | 820 | |||||||
IDRIVEP_HS or IDRIVEP_LS = 1111b | 1000 | |||||||
H/W Device | IDRIVE = Tied to AGND | 10 | ||||||
IDRIVE = 18 kΩ ± 5% tied to AGND | 30 | |||||||
IDRIVE = 75 kΩ ± 5% tied to AGND | 60 | |||||||
IDRIVE = Hi-Z | 120 | |||||||
IDRIVE = 75 kΩ ± 5% tied to DVDD | 260 | |||||||
IDRIVE = 18 kΩ ± 5% tied to DVDD | 570 | |||||||
IDRIVE = Tied to DVDD | 1000 | |||||||
IDRIVEN | Peak sink
gate current |
SPI Device | IDRIVEN_HS or IDRIVEN_LS = 0000b | 20 | mA | |||
IDRIVEN_HS or IDRIVEN_LS = 0001b | 60 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0010b | 120 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0011b | 160 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0100b | 240 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0101b | 280 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0110b | 340 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 0111b | 380 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1000b | 520 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1001b | 660 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1010b | 740 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1011b | 880 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1100b | 1140 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1101b | 1360 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1110b | 1640 | |||||||
IDRIVEN_HS or IDRIVEN_LS = 1111b | 2000 | |||||||
H/W Device | IDRIVE = Tied to AGND | 20 | ||||||
IDRIVE = 18 kΩ ± 5% tied to AGND | 60 | |||||||
IDRIVE = 75 kΩ ± 5% tied to AGND | 120 | |||||||
IDRIVE = Hi-Z | 240 | |||||||
IDRIVE = 75 kΩ ± 5% tied to DVDD | 520 | |||||||
IDRIVE = 18 kΩ ± 5% tied to DVDD | 1140 | |||||||
IDRIVE = Tied to DVDD | 2000 | |||||||
IHOLD | Gate holding current | Source current after tDRIVE | 10 | mA | ||||
Sink current after tDRIVE | 50 | |||||||
ISTRONG | Gate strong pulldown current | GHx to SHx and GLx to PGND | 2 | A | ||||
ROFF | Gate hold off resistor | GHx to SHx and GLx to PGND | 150 | kΩ | ||||
CURRENT SENSE AMPLIFIER (SNx, SOx, SPx, VREF) | ||||||||
GCSA | Amplifier gain | SPI Device | CSA_GAIN = 00b | 4.85 | 5 | 5.15 | V/V | |
CSA_GAIN = 01b | 9.7 | 10 | 10.3 | |||||
CSA_GAIN = 10b | 19.4 | 20 | 20.6 | |||||
CSA_GAIN = 11b | 38.8 | 40 | 41.2 | |||||
H/W Device | GAIN = Tied to AGND | 4.85 | 5 | 5.15 | ||||
GAIN = 47 kΩ ± 5% tied to AGND | 9.7 | 10 | 10.3 | |||||
GAIN = Hi-Z | 19.4 | 20 | 20.6 | |||||
GAIN = Tied to DVDD | 38.8 | 40 | 41.2 | |||||
tSET(1) | Settling time to ±1% | VO_STEP = 0.5 V, GCSA = 5 V/V | 150 | ns | ||||
VO_STEP = 0.5 V, GCSA = 10 V/V | 300 | |||||||
VO_STEP = 0.5 V, GVSA = 20 V/V | 600 | |||||||
VO_STEP = 0.5 V, GCSA = 40 V/V | 1200 | |||||||
VCOM | Common mode input range | –0.15 | 0.15 | V | ||||
VDIFF | Differential mode input range | –0.3 | 0.3 | V | ||||
VOFF | Input offset error | VSP = VSN = 0 V, CAL = 3.3 V, VREF = 3.3 V | –4 | 4 | mV | |||
VDRIFT(1) | Drift offset | VSP = VSN = 0 V | 10 | µV/°C | ||||
VLINEAR | SOx output voltage linear range | 0.25 | VVREF – 0.25 | V | ||||
VBIAS | SOx output voltage bias | SPI Device | VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 0b | VVREF – 0.3 | V | |||
VSP = VSN = 0 V, CAL = 3.3 V, VREF_DIV = 1b | VVREF / 2 | |||||||
H/W Device | VSP = VSN = 0 V, CAL = 3.3 V | VVREF / 2 | ||||||
IBIAS | SPx/SNx input bias current | VREF_DIV = 1b | 100 | µA | ||||
VSLEW(1) | SOx output slew rate | 60-pF load | 10 | V/µs | ||||
IVREF | VREF input current | VVREF = 5 V | 2 | 3 | mA | |||
UGB(1) | Unity gain bandwidth | 60-pF load | 1 | MHz | ||||
PROTECTION CIRCUITS | ||||||||
VUVLO | VM undervoltage lockout | VM falling, UVLO report | 5.4 | 5.6 | 5.8 | V | ||
VM rising, UVLO recovery | 5.6 | 5.8 | 6 | |||||
VUVLO_HYS | VM undervoltage hysteresis | Rising to falling threshold | 200 | mV | ||||
tUVLO_DEG | VM undervoltage deglitch time | VM falling, UVLO report | 10 | µs | ||||
VCPUV | Charge pump undervoltage lockout | VCP falling, CPUV report | VVM + 2.8 | V | ||||
VGS_CLAMP | High-side gate clamp | Positive clamping voltage | 15 | 16.5 | 18 | V | ||
Negative clamping voltage | –0.7 | |||||||
VVDS_OCP | VDS overcurrent
trip voltage |
SPI Device | VDS_LVL = 0000b | 0.06 | V | |||
VDS_LVL = 0001b | 0.13 | |||||||
VDS_LVL = 0010b | 0.2 | |||||||
VDS_LVL = 0011b | 0.26 | |||||||
VDS_LVL = 0100b | 0.31 | |||||||
VDS_LVL = 0101b | 0.45 | |||||||
VDS_LVL = 0110b | 0.53 | |||||||
VDS_LVL = 0111b | 0.6 | |||||||
VDS_LVL = 1000b | 0.68 | |||||||
VDS_LVL = 1001b | 0.75 | |||||||
VDS_LVL = 1010b | 0.94 | |||||||
VDS_LVL = 1011b | 1.13 | |||||||
VDS_LVL = 1100b | 1.3 | |||||||
VDS_LVL = 1101b | 1.5 | |||||||
VDS_LVL = 1110b | 1.7 | |||||||
VDS_LVL = 1111b | 1.88 | |||||||
H/W Device | VDS = Tied to AGND | 0.06 | ||||||
VDS = 18 kΩ ± 5% tied to AGND | 0.13 | |||||||
VDS = 75 kΩ ± 5% tied to AGND | 0.26 | |||||||
VDS = Hi-Z | 0.6 | |||||||
VDS = 75 kΩ ± 5% tied to DVDD | 1.13 | |||||||
VDS = 18 kΩ ± 5% tied to DVDD | 1.88 | |||||||
VDS = Tied to DVDD | Disabled | |||||||
tOCP_DEG | VDS and VSENSE overcurrent deglitch time | SPI Device | OCP_DEG = 00b | 2 | µs | |||
OCP_DEG = 01b | 4 | |||||||
OCP_DEG = 10b | 6 | |||||||
OCP_DEG = 11b | 8 | |||||||
H/W Device | 4 | |||||||
VSEN_OCP | VSENSE overcurrent trip voltage | SPI Device | SEN_LVL = 00b | 0.25 | V | |||
SEN_LVL = 01b | 0.5 | |||||||
SEN_LVL = 10b | 0.75 | |||||||
SEN_LVL = 11b | 1 | |||||||
H/W Device | 1 | |||||||
tRETRY | Overcurrent retry time | SPI Device | TRETRY = 0b | 4 | ms | |||
TRETRY = 1b | 50 | μs | ||||||
H/W Device | 4 | ms | ||||||
TOTW(1) | Thermal warning temperature | Die temperature, TJ | 130 | 150 | 165 | °C | ||
TOTSD(1) | Thermal shutdown temperature | Die temperature, TJ | 150 | 170 | 185 | °C | ||
THYS(1) | Thermal hysteresis | Die temperature, TJ | 20 | °C | ||||
BUCK REGULATOR SUPPLY (VIN) | ||||||||
InSHDN | Shutdown supply current | VnSHDN = 0 V | 1 | 3 | µA | |||
IQ | Operating quiescent current | VVIN = 12 V, no load; not switching | 28 | µA | ||||
VVIN_UVLO | VIN undervoltage lockout threshold | VIN Rising | 4 | V | ||||
VIN Falling | 3 | |||||||
BUCK REGULATOR SHUTDOWN (nSHDN) | ||||||||
VnSHDN_TH | Rising nSHDN threshold | 1.05 | 1.25 | 1.38 | V | |||
InSHDN | Input current | VnSHDN = 2.3 V | –4.2 | µA | ||||
VnSHDN = 0.9 V | –1 | |||||||
InSHDN_HYS | Hysteresis current | –3 | µA | |||||
BUCK REGULATOR HIGH-SIDE MOSFET | ||||||||
RDS_ON | MOSFET on resistance | VVIN = 12 V, VCB to VSW = 5.8 V, TA = 25°C | 900 | mΩ | ||||
BUCK REGULATOR VOLTAGE REFERENCE (FB) | ||||||||
VFB | Feedback voltage | 0.747 | 0.765 | 0.782 | V | |||
BUCK REGULATOR CURRENT LIMIT | ||||||||
ILIMIT | Peak current limit | VVIN = 12 V, TA = 25°C | 1200 | mA | ||||
1700 | ||||||||
BUCK REGULATOR SWITCHING (SW) | ||||||||
fSW | Switching frequency | 595 | 700 | 805 | kHz | |||
DMAX | Maximum duty cycle | 96% | ||||||
BUCK REGULATOR THERMAL SHUTDOWN | ||||||||
TSHDN(1) | Thermal shutdown threshold | 170 | °C | |||||
THYS(1) | Thermal shutdown hysteresis | 10 | °C |