JAJSDA2A June   2017  – August 2018 ESD122

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     USB Type-Cアプリケーションの例
      1.      Device Images
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  IEC 61000-4-2 ESD Protection
      2. 7.3.2  IEC 61000-4-4 EFT Protection
      3. 7.3.3  IEC 61000-4-5 Surge Protection
      4. 7.3.4  IO Capacitance
      5. 7.3.5  DC Breakdown Voltage
      6. 7.3.6  Ultra Low Leakage Current
      7. 7.3.7  Low ESD Clamping Voltage
      8. 7.3.8  Supports High Speed Interfaces
      9. 7.3.9  Industrial Temperature Range
      10. 7.3.10 Easy Flow-Through Routing Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 USB 3.1 Gen 2 Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Signal Range
          2. 8.2.1.2.2 Operating Frequency
        3. 8.2.1.3 Application Curves
      2. 8.2.2 HDMI 2.0 Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Signal Range
          2. 8.2.2.2.2 Operating Frequency
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA –3.6 3.6 V
VBRF Breakdown voltage, any IO pin to GND(1) IIO = 1 mA, TA = 25°C 5 7.9 V
VBRR Breakdown voltage, GND to any IO pin(1) IIO = 1 mA, TA = 25°C –7.9 –5 V
VHOLD Holding voltage(2) IIO = 1 mA 5.9 V
VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND, TA = 25°C 6.4 V
IPP = 5 A, TLP, from IO to GND, TA = 25°C 8.4
IPP = 1 A, TLP, from GND to IO, TA = 25°C 6.4
IPP = 5 A, TLP, from GND to IO, TA = 25°C 8.4
ILEAK Leakage current, any IO to GND VIO = ±2.5 V 10 nA
RDYN Dynamic resistance IO to GND, Measured between TLP IPP of 10 A and 20 A, TA = 25°C 0.5 Ω
GND to IO, Measured between TLP IPP of 10 A and 20 A, TA = 25°C 0.5
CL Line capacitance VIO = 0 V, f = 1 MHz, IO to GND, TA = 25°C 0.2 0.27 pF
ΔCL Variation of line capacitance Difference between the capacitance of the two IO pins measured with respect to ground, VIO = 0 V, f = 1 MHz, TA = 25°C, GND = 0 V 0.01 pF
CCROSS Channel to channel capacitance Capacitance from one IO to another IO, VIO = 0 V, f = 1 MHz, TA = 25°C,
GND = 0 V		 0.1 0.14 pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state.
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.