SBOS743A July   2015  – May 2020 INA226-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      High-Side or Low-Side Sensing Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic ADC Functions
        1. 7.3.1.1 Power Calculation
        2. 7.3.1.2 Alert Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Averaging and Conversion Time Considerations
      2. 7.4.2 Filtering and Input Considerations
    5. 7.5 Programming
      1. 7.5.1 Programming the Calibration Register
      2. 7.5.2 Programming the Power Measurement Engine
        1. 7.5.2.1 Calibration Register and Scaling
      3. 7.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
      4. 7.5.4 Default Settings
      5. 7.5.5 Bus Overview
        1. 7.5.5.1 Serial Bus Address
        2. 7.5.5.2 Serial Interface
        3. 7.5.5.3 Writing to and Reading from the INA226-Q1
          1. 7.5.5.3.1 High-Speed I2C Mode
        4. 7.5.5.4 SMBus Alert Response
    6. 7.6 Register Maps
      1. Table 4. Register Set Summary
      2. 7.6.1    Configuration Register (00h) (Read/Write)
        1. Table 5. Configuration Register (00h) (Read/Write) Descriptions
      3. 7.6.2    Shunt Voltage Register (01h) (Read-Only)
        1. Table 10. Shunt Voltage Register (01h) (Read-Only) Description
      4. 7.6.3    Bus Voltage Register (02h) (Read-Only)
        1. Table 11. Bus Voltage Register (02h) (Read-Only) Description
      5. 7.6.4    Power Register (03h) (Read-Only)
        1. Table 12. Power Register (03h) (Read-Only) Description
      6. 7.6.5    Current Register (04h) (Read-Only)
        1. Table 13. Current Register (04h) (Read-Only) Register Description
      7. 7.6.6    Calibration Register (05h) (Read/Write)
        1. Table 14. Calibration Register (05h) (Read/Write) Description
      8. 7.6.7    Mask/Enable Register (06h) (Read/Write)
        1. Table 15. Mask/Enable Register (06h) (Read/Write)
      9. 7.6.8    Alert Limit Register (07h) (Read/Write)
        1. Table 16. Alert Limit Register (07h) (Read/Write) Description
      10. 7.6.9    Manufacturer ID Register (FEh) (Read-Only)
        1. Table 17. Manufacturer ID Register (FEh) (Read-Only) Description
      11. 7.6.10   Die ID Register (FFh) (Read-Only)
        1. Table 18. Die ID Register (FFh) (Read-Only) Description
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Sensing Circuit Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
          1. Table 19. Configuration Register (00h) Settings for (Value = 4025h)
          2. Table 20. Configuration Register (00h) Settings for (Value = 4005h)
          3. Table 21. Mask/Enable Register (06h) Settings for and (Value = 8000h)
          4. Table 22. Alert Limit Register (07h) Settings for and (Value = 7D00)
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.5.1 Serial Bus Address

To communicate with the INA226-Q1, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.

The device has two address pins, A0 and A1. Table 2 lists the pin logic levels for each of the 16 possible addresses. The device samples the state of pins A0 and A1 on every bus communication. Establish the pin states before any activity on the interface occurs.

Table 2. Address Pins and Slave Addresses

A1 A0 SLAVE ADDRESS
GND GND 1000000
GND VS 1000001
GND SDA 1000010
GND SCL 1000011
VS GND 1000100
VS VS 1000101
VS SDA 1000110
VS SCL 1000111
SDA GND 1001000
SDA VS 1001001
SDA SDA 1001010
SDA SCL 1001011
SCL GND 1001100
SCL VS 1001101
SCL SDA 1001110
SCL SCL 1001111