JAJSMK7C December   2013  – July 2021 LMK00338

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Crystal Power Dissipation vs. RLIM
      2. 8.3.2 Clock Inputs
      3. 8.3.3 Clock Outputs
        1. 8.3.3.1 Reference Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 VCC and VCCO Power Supplies
  9. 9 Power Supply Recommendations
    1. 9.1 Current Consumption and Power Dissipation Calculations
      1. 9.1.1 Power Dissipation Example: Worst-Case Dissipation
    2. 9.2 Power Supply Bypassing
      1. 9.2.1 Power Supply Ripple Rejection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.2 Crystal Interface

The LMK00338 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 9-5.

GUID-75FD3EC3-C894-4557-8369-8968C36611AE-low.gifFigure 9-5 Crystal Interface

The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY = 1 to approximately 3 pF) can affect the discrete load capacitor values, C1 and C2.

For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:

Equation 1. CL = (C1 × C2) / (C1 + C2) + CIN + CSTRAY

Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1 only:

Equation 2. CL = C12 / (2 × C1) + CIN + CSTRAY

Finally, solve for C1:

Equation 3. C1 = (CL – CIN – CSTRAY) × 2

The Electrical Characteristics table provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer must ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start up and maintain steady-state operation.

The power dissipated in the crystal, PXTAL, can be computed by:

Equation 4. PXTAL = IRMS2 × RESR × (1 + C0/CL)2

where

  • IRMS is the RMS current through the crystal.
  • RESR is the maximum equivalent series resistance specified for the crystal
  • CL is the load capacitance specified for the crystal
  • C0 is the minimum shunt capacitance specified for the crystal

IRMS can be measured using a current probe (for example, Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active.

As shown in Figure 9-5, an external resistor, RLIM, can be used to limit the crystal drive level, if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 kΩ.