JAJSG13G October 2012 – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VR+ | Positive external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit | VR+ > VR– | 1.2 | AVCC | V | |
VR– | Negative external reference voltage input VeREF+ or VeREF- based on ADC12VRSEL bit | VR+ > VR– | 0 | 1.2 | V | |
VR+ – VR– | Differential external reference voltage input | VR+ > VR– | 1.2 | AVCC | V | |
IVeREF+,
IVeREF- |
Static input current, singled-ended input mode | 1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 0, ADC12PWRMD = 0 |
±10 | µA | ||
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 0, ADC12PWRMD = 01 |
±2.5 | |||||
IVeREF+,
IVeREF- |
Static input current, differential input mode | 1.2 V ≤ VeREF+ ≤ VAVCC, VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 1h, ADC12DIF = 1, ADC12PWRMD = 0 |
±20 | µA | ||
1.2 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V
fADC12CLK = 5 MHz, ADC12SHTx = 8h, ADC12DIF = 1, ADC12PWRMD = 1 |
±5 | |||||
IVeREF+ | Peak input current with single-ended input | 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 0 | 1.5 | mA | ||
IVeREF+ | Peak input current with differential input | 0 V ≤ VeREF+ ≤ VAVCC, ADC12DIF = 1 | 3 | mA | ||
CVeREF+/- | Capacitance at VeREF+ or VeREF- terminal | See (2) | 10 | µF |