JAJSDQ7C June 2017 – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PLL_CLKin | Input clock to HSPLL | 4 | 8 | MHz | ||
PLL_CLKout | Output clock from HSPLL | 68 | 80 | MHz | ||
LOCKpwr | Lock time from PLL power up | Reference clock = PLL_CLKin,
Sequence: Set USS.CTL.USSPWRUP bit = 1, then measure the time between PSQ_PLLUP (internal control signal) is set to 1 and HSPLL.CTL.PLL_LOCK is set to 1 |
64 | cycles |
Table 5-38 lists the characteristics of the USS SDHS.