at TA =
25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2, unless
otherwise noted.
Figure 7-39 Offset Voltage
Production Distribution
Figure 7-41 Offset Voltage
vs Temperature (PMOS Input Pair)![Offset Voltage
vs Common-Mode Voltage (Full Range) GUID-0A29C3A3-6B2E-4ACE-A5BF-F3E788319512-low.gif](/ods/images/JAJSE51E/GUID-0A29C3A3-6B2E-4ACE-A5BF-F3E788319512-low.gif)
Over full common-mode
voltage range |
Figure 7-43 Offset Voltage
vs Common-Mode Voltage (Full Range)
Figure 7-45 Offset Voltage
vs Common-Mode Voltage (Transition Region)
Figure 7-47 IB
and IOS vs Common-Mode Voltage
Figure 7-49 0.1-Hz to 10-Hz
Flicker Noise
Figure 7-51 CMRR and PSRR
vs Frequency (Referred to Input)
Figure 7-53 PSRR vs
Temperature
Figure 7-55 Closed-Loop
Gain vs Frequency
Figure 7-57 Open-Loop Gain
vs Output Voltage
Figure 7-59 No Phase
Reversal![Small-Signal
Overshoot vs Load Capacitance GUID-7B0FFA05-FC70-4EF3-826C-072B1336DA9F-low.gif](/ods/images/JAJSE51E/GUID-7B0FFA05-FC70-4EF3-826C-072B1336DA9F-low.gif)
VCM =
VS / 2, RL = 1 kΩ |
Gain = +1, 100-mV output
step |
Figure 7-61 Small-Signal
Overshoot vs Load Capacitance![Small-Signal
Step Response GUID-3D94389D-44CA-4C4C-9D1D-CA9FF9C8AC02-low.gif](/ods/images/JAJSE51E/GUID-3D94389D-44CA-4C4C-9D1D-CA9FF9C8AC02-low.gif)
CL = 20
pF, Gain = 1, VIN = 100-mVpp, RL = 1 kΩ |
Figure 7-63 Small-Signal
Step Response![Large Signal
Step Response GUID-2926DEC4-B457-4055-BEB0-C220CA23F804-low.gif](/ods/images/JAJSE51E/GUID-2926DEC4-B457-4055-BEB0-C220CA23F804-low.gif)
CL = 20 pF,
Gain = +1, VIN = 2-V step, RL = 1 kΩ |
Figure 7-65 Large Signal
Step Response![Large Signal
Settling Time (Positive) GUID-31314C61-A311-44FA-AE80-66F91A87B51D-low.gif](/ods/images/JAJSE51E/GUID-31314C61-A311-44FA-AE80-66F91A87B51D-low.gif)
CL = 20 pF,
Gain = 1, VIN = 2-V step |
Figure 7-67 Large Signal
Settling Time (Positive)![THD + N vs
Frequency GUID-51638D7C-2BF3-4E87-B5DE-8D1314CEC539-low.gif](/ods/images/JAJSE51E/GUID-51638D7C-2BF3-4E87-B5DE-8D1314CEC539-low.gif)
VCM = 2.5
V |
Gain = +1, BW = 80 kHz,
VOUT = 0.5 Vrms |
Figure 7-69 THD + N vs
Frequency
Figure 7-71 VOUT
vs Sourcing Current![Maximum Output
Voltage vs Frequency GUID-AF290717-FE87-4C7E-AC5E-054EEBAD08FA-low.gif](/ods/images/JAJSE51E/GUID-AF290717-FE87-4C7E-AC5E-054EEBAD08FA-low.gif)
CL = 10 pF,
Gain = +1, VS= 5.5 V |
Figure 7-73 Maximum Output
Voltage vs Frequency
Figure 7-75 Quiescent
Current vs Supply Voltage
Figure 7-77 Open-Loop
Output Impedance vs Frequency
Figure 7-79 Electromagnetic
Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs
Frequency
Figure 7-40 Offset Voltage
Drift Distribution
Figure 7-42 Offset Voltage
vs Temperature (NMOS Input Pair)
Figure 7-44 Offset Voltage
vs Common-Mode Voltage (PMOS Input Pair)
Figure 7-46 Offset Voltage
vs Power Supply
Figure 7-48 IB
and IOS vs Temperature
Figure 7-50 Input Voltage
Noise Spectral Density vs Frequency![CMRR vs
Temperature GUID-04B2576E-966C-4633-BE5C-F945AAA8FE3E-low.gif](/ods/images/JAJSE51E/GUID-04B2576E-966C-4633-BE5C-F945AAA8FE3E-low.gif)
VS = 5.5 V,
VCM = V– to (V+) – 1.2 V |
Figure 7-52 CMRR vs
Temperature
Figure 7-54 Open-Loop Gain
and Phase vs Frequency
Figure 7-56 Open-Loop Gain
vs Temperature
Figure 7-58 Phase Margin vs
Capacitive Load![Small-Signal
Overshoot vs Load Capacitance GUID-1214C308-9A26-44A0-85F8-D8281CFA1194-low.gif](/ods/images/JAJSE51E/GUID-1214C308-9A26-44A0-85F8-D8281CFA1194-low.gif)
VCM =
VS / 2, RL = 1 kΩ |
Gain = –1, 100-mV output
step |
Figure 7-60 Small-Signal
Overshoot vs Load Capacitance![Overload
Recovery GUID-CE13C3C3-F94D-4015-894B-80308FA2EE82-low.gif](/ods/images/JAJSE51E/GUID-CE13C3C3-F94D-4015-894B-80308FA2EE82-low.gif)
VIN = 0.6
Vpp, G = –10, VIN × gain > VS |
|
|
|
Figure 7-62 Overload
Recovery![Small-Signal
Step Response GUID-BEEAFB47-078A-4C14-BF56-4DC2569031F5-low.gif](/ods/images/JAJSE51E/GUID-BEEAFB47-078A-4C14-BF56-4DC2569031F5-low.gif)
CL = 20
pF, Gain = –1, VIN = 100-mVpp, RL = 1 kΩ |
Figure 7-64 Small-Signal
Step Response![Large Signal
Step Response GUID-FC1AFAD3-BA25-4A38-857D-D09AF1885E26-low.gif](/ods/images/JAJSE51E/GUID-FC1AFAD3-BA25-4A38-857D-D09AF1885E26-low.gif)
CL = 20 pF,
Gain = –1, VIN = 2-V step, RL = 1 kΩ |
Figure 7-66 Large Signal
Step Response![Large Signal
Settling Time (Negative) GUID-ED00221E-5F06-41E5-9A7A-FA0DDB5FC846-low.gif](/ods/images/JAJSE51E/GUID-ED00221E-5F06-41E5-9A7A-FA0DDB5FC846-low.gif)
CL = 20 pF,
Gain = –1, VIN = 2-V step |
Figure 7-68 Large Signal
Settling Time (Negative)
Figure 7-70 THD + N vs
Amplitude
Figure 7-72 VOUT
vs Sinking Current
Figure 7-74 Short-Circuit
Current vs Temperature
Figure 7-76 Quiescent
Current vs Temperature![Channel
Separation vs Frequency GUID-C3193C41-4033-42E5-AA41-57AD0413CAB4-low.gif](/ods/images/JAJSE51E/GUID-C3193C41-4033-42E5-AA41-57AD0413CAB4-low.gif)
AVDD = 5.5 V,
VICM = VOCM = 2.75 V |
Figure 7-78 Channel
Separation vs Frequency![Turn-On
Time GUID-4AFFB029-64CD-4FBC-8048-A3A8D8D4C47F-low.gif](/ods/images/JAJSE51E/GUID-4AFFB029-64CD-4FBC-8048-A3A8D8D4C47F-low.gif)
VS = 0 to 5.5
V, VOUT = 0 to 2.75 V |
Figure 7-80 Turn-On
Time