JAJS199E
April 2003 – July 2019
PCM1753
,
PCM1754
,
PCM1755
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
機能ブロック図
4
改訂履歴
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
System Clock Input Timing
7.7
Audio Interface Timing
7.8
Control Interface Timing Requirements
7.9
Typical Characteristics
7.9.1
Digital Filter (De-Emphasis Off)
7.9.2
Analog Dynamic Performance (Supply Voltage Characteristics)
7.9.3
Analog Dynamic Performance (Temperature Characteristics)
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
System Clock and Reset Functions
8.3.1.1
System Clock Input
8.3.1.2
Power-On Reset Functions
8.3.2
Audio Serial Interface
8.3.2.1
Audio Data Formats and Timing
8.3.3
Zero Flag (PCM1754)
8.3.4
Zero Flag (PCM1753)
8.3.5
Zero Flag Outputs
8.3.6
Analog Outputs
8.3.6.1
VCOM Output
8.4
Device Functional Modes
8.4.1
Hardware Control (PCM1754)
8.4.2
Oversampling Rate Control (PCM1754)
8.5
Programming
8.5.1
Software Control (PCM1753/55)
8.5.1.1
Register Write Operation
8.6
Register Maps
8.6.1
Mode Control Registers (PCM1753/55)
8.6.1.1
User-Programmable Mode Controls
8.6.1.2
Register Definitions
8.6.1.2.1
ATx[7:0]: Digital Attenuation Level Setting
8.6.1.2.2
MUTx: Soft Mute Control
8.6.1.2.3
OVER: Oversampling Rate Control
8.6.1.2.4
SRST: Reset
8.6.1.2.5
DACx: DAC Operation Control
8.6.1.2.6
DM12: Digital De-Emphasis Function Control
8.6.1.2.7
DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
8.6.1.2.8
FMT[2:0]: Audio Interface Data Format
8.6.1.2.9
FLT: Digital Filter Rolloff Control
8.6.1.2.10
DREV: Output Phase Select
8.6.1.2.11
ZREV: Zero Flag Polarity Select
8.6.1.2.12
AZRO: Zero Flag Function Select
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Design Parameters
9.2.1.2
Power Supplies and Grounding
9.2.1.3
D/A Output Filter Circuits
9.2.2
Detailed Design Procedure
9.2.2.1
Total Harmonic Distortion + Noise
9.2.2.2
Dynamic Range
9.2.2.3
Idle Channel Signal-to-Noise Ratio (SNR)
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
デバイスおよびドキュメントのサポート
12.1
関連資料
12.2
関連リンク
12.3
ドキュメントの更新通知を受け取る方法
12.4
コミュニティ・リソース
12.5
商標
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DBQ|16
MSOI004H
サーマルパッド・メカニカル・データ
発注情報
jajs199e_oa
jajs199e_pm
9.2.3
Application Curves
Figure 35.
Quantization Noise Spectrum (×64 Oversampling)
Figure 37.
Jitter Dependence (×64 Oversampling)
Figure 36.
Quantization Noise Spectrum (×128 Oversampling)