SLLS980E
June 2009 – November 2016
SN75LVDS83A
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Dissipation Ratings
7.7
Timing Requirements
7.8
Switching Characteristics
7.9
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
TTL Input Data
9.3.2
LVDS Output Data
9.4
Device Functional Modes
9.4.1
Input Clock Edge
9.4.2
Low Power Mode
10
Application and Implementation
10.1
Application Information
10.1.1
Signal Connectivity
10.1.2
PCB Routing
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Power Up Sequence
10.2.3
Application Curve
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Board Stackup
12.1.2
Power and Ground Planes
12.1.3
Traces, Vias, and Other PCB Components
12.2
Layout Example
13
Device and Documentation Support
13.1
Receiving Notification of Documentation Updates
13.2
Community Resources
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DGG|56
MPDS570
サーマルパッド・メカニカル・データ
発注情報
slls980e_oa
slls980e_pm
8
Parameter Measurement Information
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0 V.
Figure 5.
Set Up and Hold Time Definition
Figure 6.
Test Load and Voltage Definitions for LVDS Outputs
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 7.
16 Grayscale Test Pattern
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 8.
Worst-Case Power Test Pattern
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 9.
SN75LVDS83A Timing Definitions
Figure 10.
Output Clock Jitter Test Set Up
Figure 11.
Enable Time Waveforms
Figure 12.
Disable Time Waveforms