JAJSFF9B March 2016 – May 2018 TAS5751M
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCLKIN | Frequency, SCLK 32 × fS, 48 × fS, 64 × fS | CL ≤ 30 pF | 1.024 | 12.288 | MHz | |
tsu1 | Setup time, LRCK to SCLK rising edge | 10 | ns | |||
th1 | Hold time, LRCK from SCLK rising edge | 10 | ns | |||
tsu2 | Setup time, SDIN to SCLK rising edge | 10 | ns | |||
th2 | Hold time, SDIN from SCLK rising edge | 10 | ns | |||
LRCK frequency | 8 | 48 | 48 | kHz | ||
SCLK duty cycle | 40% | 50% | 60% | |||
LRCK duty cycle | 40% | 50% | 60% | |||
SCLK rising edges between LRCK rising edges | 32 | 64 | SCLK edges | |||
t(edge) | LRCK clock edge with respect to the falling edge of SCLK | –1/4 | 1/4 | SCLK period | ||
tr/tf | Rise/fall time for SCLK/LRCK | 8 | ns | |||
LRCK allowable drift before LRCK reset | 4 | MCLKs |
NOTE:
On power up, hold the TAS5751M RST LOW for at least 100 μs after DVDD has reached 3 V.NOTE:
If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).