SPRS614F March 2011 – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168
PRODUCTION DATA.
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There are variations in the availability of some functions of the TMS320DM816x devices. A comparison of the devices, highlighting the differences, is shown in Table 3-1. For more detailed information on the significant device features, see Section 3.1, Device Characteristics.
FEATURES | DEVICES | ||
---|---|---|---|
TMS320DM8168 | TMS320DM8167 | TMS320DM8165 | |
HDVICP2 | 3 | 3 | 2 |
SGX530 | Y | N | N |
Table 3-2 provides an overview of the significant features of the TMS320DM816xdevices, including the capacity of on-chip RAM, peripherals, and the package type with pin count.
HARDWARE FEATURES | DM8168, DM6187, and DM6185 | ||
---|---|---|---|
Peripherals Not all peripherals pins are available at the same time (for more detail, see Section 6, Device Configurations). |
HD Video Processing Subsystem (HDVPSS) | 1 16-bit and 24-bit HD Capture Channel or
2 8-bit SD Capture Channels and 1 16-bit HD Capture Channel or 2 8-bit SD Capture Channels and 1 16-bit, 24-bit, and 32-bit HD Display Channel and 1 16-bit HD Display Channel and 3 HD and 4 SD Video DACs and 1 HDMI 1.3 Transmitter |
|
DDR2 and DDR3 Memory Controller | 2 (32-bit Bus Widths) | ||
GPMC and ELM | Asynchronous (8-bit and 16-bit bus width) RAM, NOR, NAND | ||
EDMA | 64 Independent Channels 8 QDMA Channels |
||
10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MAC with Management Data Input and Output (MDIO) | 2 (with MII and GMII Interface) | ||
USB 2.0 | 2 (Supports High-Speed and Full-Speed as a Device and High-Speed, Full-Speed, and Low-Speed as a Host) | ||
PCI Express 2.0 | 1 Port (2 5.0GT per second lanes) | ||
Timers | 7 (32-bit General Purpose) and 1 (Watchdog) |
||
UART | 3 (with SIR, MIR, CIR support and RTS and CTS flow control) (UART0 Supports Modem Interface) |
||
SPI | 1 (Supports 4 slave devices) | ||
SD and SDIO | 1 (1-bit or 4-bit) | ||
I2C | 2 (Master or Slave) | ||
McASP | 3 (1 Six-Serializer and 2 Dual Serializers, Each with Transmit and Receive and DIT Capability) | ||
McBSP | 1 (2 Data Pins, Transmit and Receive) | ||
Serial ATA (SATA) | Supports 2 Interfaces | ||
RTC | 1 | ||
GPIO | Up to 64 pins | ||
On-Chip Memory | Organization | ARM
32KB I-cache 32KB D-cache 256KB L2 Cache 64KB RAM 48KB Boot ROM |
|
DSP
32KB L1 Program (L1P) and Cache (up to 32KB) 32KB L1 Data (L1D) and Cache (up to 32KB) 256KB Unified Mapped RAM and Cache (L2) |
|||
MEDIA CONTROLLER
32KB Shared L1 Cache 256KB L2 RAM |
|||
ADDITIONAL SHARED MEMORY
512KB On-chip RAM |
|||
CPU ID + CPU Rev ID | Control Status Register (CSR.[31:16]) | 0x1003 | |
C674x Megamodule Revision | Revision ID Register (MM_REVID[15:0]) | 0x0000 | |
JTAG BSDL_ID | JTAGID Register | 0x2B81 E02F | |
CPU Frequency(1) | MHz | Blank | ARM Cortex-A8: 930 MHz |
DSP: 750 MHz | |||
2 | ARM Cortex-A8: 1100 MHz | ||
DSP: 930 MHz | |||
4 | ARM Cortex-A8: 1200 MHz | ||
DSP: 1000 MHz | |||
Voltage | Core Logic (V) | 1.0 V with Required AVS Capability | |
USB Logic (V) | 0.9 V | ||
RAM (V) | 1.0 V | ||
IO (V) | 1.5 V, 1.8 V, 3.3 V | ||
Package | 25 x 25 mm | 1031-Pin BGA (CYG) | |
Process Technology | µm | 0.04 µm | |
Product Status(1) | Product Preview (PP), Advance Information (AI), or Production Data (PD) |
PD |
The ARM subsystem is designed to give the ARM Cortex-A8 master control of the device. In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystem, peripherals, and external memories.
The ARM subsystem includes the following features:
The ARM Cortex-A8 subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose processors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including:
To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts:
The ARM Cortex-A8 trace port is connected to the system-level embedded trace buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read and interpret the captured trace data.
For more details on the ETB, see Section 9.4.2.
The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 8.4.
The ARM Cortex-A8 processor in connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules.
The DSP Subsystem includes the following features:
The C674x central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-3. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add and subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add and subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add and subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit and 16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.
Other new features include:
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:
All C674x DSP accesses through the MDMA port are directed through the system memory management unit (System MMU) module where they are remapped to physical system addresses. This protects the ARM Cortex-A8 memory regions from accidental corruption by C674x code and allows for direct allocation of buffers in user space without the need for translation between ARM and DSP applications.
In addition, accesses by the EDMA TC0 may optionally be routed through the System MMU. This allows EDMA Channel 0 to be used by the DSP to perform transfers using only the known virtual addresses of the associated buffers. The MMU_CFG register in the Control Module is used to enable and disable use of the DSP EDMA MMU by the EDMA TC.
For details on the System MMU features and registers, see the System MMU chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).
Table 3-3 lists the System MMU registers.
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4801 0000h | MMU_REVISION | Revision |
0x4801 0010h | MMU_SYSCONFIG | Configuration |
0x4801 0014h | MMU_SYSSTATUS | Status |
0x4801 0018h | MMU_IRQSTATUS | IRQ Status |
0x4801 001Ch | MMU_IRQENABLE | IRQ Enable |
0x4801 0040h | MMU_WALKING_ST | Table Walking Logic |
0x4801 0044h | MMU_CNTL | Control |
0x4801 0048h | MMU_FAULT_AD | Fault Address |
0x4801 004Ch | MMU_TTB | Translation Table Base Address |
0x4801 0050h | MMU_LOCK | Lock |
0x4801 0054h | MMU_LD_TLB | Load |
0x4801 0058h | MMU_CAM | CAM |
0x4801 005Ch | MMU_RAM | RAM |
0x4801 0060h | MMU_GFLUSH | Global Flush |
0x4801 0064h | MMU_FLUSH_ENTRY | Flush Entry |
0x4801 0068h | MMU_READ_CAM | Read CAM |
0x4801 006Ch | MMU_READ_RAM | Read RAM |
0x4801 0070h | MMU_EMU_FAULT_AD | EMU Fault Address |
0x4801 0080h | MMU_FAULT_PC | Fault Program Counter |
The Media Controller has the responsibility of managing the HDVPSS and HDVICP2 modules.
The HDVICP2 is a video encoder and decoder hardware accelerator supporting a range of encode and decode operations at up to 1080p60 for most major video codec standards. Transcode operations are also supported. The main video codec standards supported in hardware are MPEG1, MPEG2 and MPEG4 ASP and SP, H.264 BL, MP, and HP, VC-1 SP, MP, and AP, RV9 and RV10, AVS-1.0, and ON2 VP6.2 and VP7. The HDVICP2 hardware accelerator is composed of the following elements:
This device is a multi-core device that requires software to efficiently manage and communicate between the cores. The following are the main features that need to be implemented by such software:
On this device, the host processor is usually the ARM Cortex-A8. This processor is responsible for bootloading the slave processors (C674x). Bootloading includes power management of the slaves (powerup and powerdown and other power management), reset control (reset and release of the slave processor) and setting the entry point of the slave executable into the appropriate register. This device has a power-on reset (POR) and warm reset. For the POR reset, the ARM Cortex-A8 is taken out of reset and it boots from its boot ROM. Once booted, the ARM Cortex-A8 bootloads the C674x processor.
For implementing efficient inter-processor communication between the multiple cores on the device, the following hardware features are provided:
Mailboxes provide a mechanism for one processor to write a value to a register and send an interrupt to another processor. Spinlocks facilitate access to shared resources in the system.
The device Mailbox module facilitates communication between the ARM Cortex-A8, C674x DSP, and the Media Controller. It consists of twelve mailboxes, each supporting communication between two of the above processors. The sender sends information to the receiver by writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation.
The Mailbox module supports the following features (see Figure 3-4):
Table 3-4 lists the Mailboxes available on this device. The register set below is applicable to these mailboxes. Table 3-5 lists the Mailbox registers.
MAILBOX TYPE | USER NUMBER (u) | MAILBOX NUMBER (m) | MESSAGES PER MAILBOX |
---|---|---|---|
System Mailbox | 0 to 3 | 0 to 11 | 4 |
HDVICP2-0 Mailbox | 0 to 3 | 0 to 5 | 4 |
HDVICP2-1Mailbox | 0 to 3 | 0 to 5 | 4 |
HDVICP2-2 Mailbox | 0 to 3 | 0 to 5 | 4 |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x480C 8000 | MAILBOX_REVISION | Mailbox Revision |
0x480C 8010 | MAILBOX_SYSCONFIG | Mailbox System Configuration |
0x480C 8040 + (0x4 * m) | MAILBOX_MESSAGE_m | Mailbox Message |
0x480C 8080 + (0x4 * m) | MAILBOX_FIFOSTATUS_m | Mailbox FIFO Status |
0x480C 80C0 + (0x4 * m) | MAILBOX_MSGSTATUS_m | Mailbox Message Status |
0x480C 8100 + (0x10 * u) | MAILBOX_IRQSTATUS_RAW_u | Mailbox IRQ RAW Status |
0x480C 8104 + (0x10 * u) | MAILBOX_IRQSTATUS_CLR_u | Mailbox IRQ Clear Status |
0x480C 8108 + (0x10 * u) | MAILBOX_IRQENABLE_SET_u | Mailbox IRQ Enable Set |
0x480C 810C + (0x10 * u) | MAILBOX_IRQENABLE_CLR_u | Mailbox IRQ Enable Clear |
0x480C 8140 | - | Reserved |
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device:
The Spinlock module implements 64 spinlocks (or hardware semaphores) that provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need for a read-modify-write bus transfer of which the programmable cores are not capable.
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x480C A000 | SPINLOCK_REV | Revision |
0x480C A010h | SPINLOCK_SYSCFG | System Configuration |
0x480C A014h | SPINLOCK_SYSSTAT | System Status |
0x480C A800 + (0x4*i) | SPINLOCK_LOCK_REG_i | Lock |
The PRCM module is the centralized management module for the power, reset, and clock control signals of the device. It interfaces with all the components on the device for power, clock, and reset management through power-control signals. It integrates enhanced features to allow the device to adapt energy consumption dynamically, according to changing application and performance requirements. The innovative hardware architecture allows a substantial reduction in leakage current.
The PRCM module is composed of two main entities:
Table 3-7 lists the physical addresses of the PRM and CM modules. Table 3-8 through Table 3-25 provide register mapping summaries of the PRM and CM registers.
For more details on the PRCM, see Section 8 of this data sheet, Power, Reset, Clocking and Interrupts, and the PRCM chapter of the TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual (literature number SPRUGX8).
ADDRESS OFFSET | MODULE NAME | SIZE | SEE |
---|---|---|---|
0x0000 | PRM_DEVICE | 256 Bytes | Table 3-8 |
0x0100 | CM_DEVICE | 256 Bytes | Table 3-9 |
0x0300 | CM_DPLL | 256 Bytes | Table 3-11 |
0x0400 | CM_ACTIVE | 256 Bytes | Table 3-12 |
0x0500 | CM_DEFAULT | 256 Bytes | Table 3-13 |
0x0600 | CM_IVAHD0 | 256 Bytes | Table 3-14 |
0x0700 | CM_IVAHD1 | 256 Bytes | Table 3-15 |
0x0800 | CM_IVAHD2 | 256 Bytes | Table 3-16 |
0x0900 | CM_SGX | 256 Bytes | Table 3-17 |
0x0A00 | PRM_ACTIVE | 256 Bytes | Table 3-18 |
0x0B00 | PRM_DEFAULT | 256 Bytes | Table 3-19 |
0x0C00 | PRM_IVAHD0 | 256 Bytes | Table 3-20 |
0x0D00 | PRM_IVAHD1 | 256 Bytes | Table 3-21 |
0x0E00 | PRM_IVAHD2 | 256 Bytes | Table 3-22 |
0x0F00 | PRM_SGX | 256 Bytes | Table 3-23 |
0x1400 | CM_ALWON | 1 KBytes | Table 3-24 |
0x1800 | PRM_ALWON | 1 KBytes | Table 3-25 |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 00A0 | PRM_RSTCTRL | Global software cold and warm reset control |
0x4818 00A4 | PRM_RSTTIME | Reset duration control |
0x4818 00A8 | PRM_RSTST | Global reset sources log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0100 | CM_CLKOUT_CTRL | SYS_CCCLKOUT output control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0200 | REVISION_PRM | PRCM IP revision code |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0300 | CM_SYSCLK1_CLKSEL | SYSCLK1 clock divider value select |
0x4818 0304 | CM_SYSCLK2_CLKSEL | SYSCLK2 clock divider value select |
0x4818 0308 | CM_SYSCLK3_CLKSEL | SYSCLK3 clock divider value select |
0x4818 030C | CM_SYSCLK4_CLKSEL | SYSCLK4 clock divider value select |
0x4818 0310 | CM_SYSCLK5_CLKSEL | SYSCLK5 clock divider value select |
0x4818 0314 | CM_SYSCLK6_CLKSEL | SYSCLK6 clock divider value select |
0x4818 0318 | CM_SYSCLK7_CLKSEL | SYSCLK7 clock divider value select |
0x4818 0324 | CM_SYSCLK10_CLKSEL | SYSCLK10 clock divider value select |
0x4818 032C | CM_SYSCLK11_CLKSEL | SYSCLK11 clock divider value select |
0x4818 0334 | CM_SYSCLK13_CLKSEL | SYSCLK13 clock divider value select |
0x4818 0338 | CM_SYSCLK15_CLKSEL | SYSCLK15 clock divider value select |
0x4818 0340 | CM_VPB3_CLKSEL | Video PLL B3 clock divider value select |
0x4818 0344 | CM_VPC1_CLKSEL | Video PLL C1 clock divider value select |
0x4818 0348 | CM_VPD1_CLKSEL | Video PLL D1 clock divider value select |
0x4818 034C | CM_SYSCLK19_CLKSEL | SYSCLK19 clock divider value select |
0x4818 0350 | CM_SYSCLK20_CLKSEL | SYSCLK20 clock divider value select |
0x4818 0354 | CM_SYSCLK21_CLKSEL | SYSCLK21 clock divider value select |
0x4818 0358 | CM_SYSCLK22_CLKSEL | SYSCLK22 clock divider value select |
0x4818 035C | CM_APA_CLKSEL | Audio PLL A clock divider value select |
0x4818 0370 | CM_SYSCLK14_CLKSEL | SYSCLK14 clock mux select line |
0x4818 0374 | CM_SYSCLK16_CLKSEL | SYSCLK16 clock mux select line |
0x4818 0378 | CM_SYSCLK18_CLKSEL | SYSCLK18 clock mux select line |
0x4818 037C | CM_AUDIOCLK_MCASP0_CLKSEL | McASP0 audio clock mux select line |
0x4818 0380 | CM_AUDIOCLK_MCASP1_CLKSEL | McASP1 audio clock mux select line |
0x4818 0384 | CM_AUDIOCLK_MCASP2_CLKSEL | McASP2 audio clock mux select line |
0x4818 0388 | CM_AUDIOCLK_MCBSP_CLKSEL | McBSP audio clock mux select line |
0x4818 0390 | CM_TIMER1_CLKSEL | Timer1 clock mux select line |
0x4818 0394 | CM_TIMER2_CLKSEL | Timer2 clock mux select line |
0x4818 0398 | CM_TIMER3_CLKSEL | Timer3 clock mux select line |
0x4818 039C | CM_TIMER4_CLKSEL | Timer4 clock mux select line |
0x4818 03A0 | CM_TIMER5_CLKSEL | Timer5 clock mux select line |
0x4818 03A4 | CM_TIMER6_CLKSEL | Timer6 clock mux select line |
0x4818 03A8 | CM_TIMER7_CLKSEL | Timer7 clock mux select line |
0x4818 03B0 | CM_SYSCLK23_CLKSEL | SYSCLK23 clock divider value select |
0x4818 03B4 | CM_SYSCLK24_CLKSEL | SYSCLK24 clock divider value select |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0400 | CM_GEM_CLKSTCTRL | DSP clock domain power state transition |
0x4818 0404 | CM_HDDSS_CLKSTCTRL | HDVPSS clock domain power state transition |
0x4818 0408 | CM_HDMI_CLKSTCTRL | HDMI clock domain power state transition |
0x4818 0420 | CM_ACTIVE_GEM_CLKCTRL | DSP clock management control |
0x4818 0424 | CM_ACTIVE_HDDSS_CLKCTRL | HDVPSS clock management control |
0x4818 0428 | CM_ACTIVE_HDMI_CLKCTRL | HDMI clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0504 | CM_DEFAULT_L3_MED_CLKSTCTRL | L3 clock domain power state transition |
0x4818 0508 | CM_DEFAULT_L3_FAST_CLKSTCTRL | L3 clock domain power state transition |
0x4818 0510 | CM_DEFAULT_PCI_CLKSTCTRL | PCI clock domain power state transition |
0x4818 0514 | CM_DEFAULT_L3_SLOW_CLKSTCTRL | L3 clock domain power state transition |
0x4818 0520 | CM_DEFAULT_EMIF_0_CLKCTRL | EMIF0 clock management control |
0x4818 0524 | CM_DEFAULT_EMIF_1_CLKCTRL | EMIF1 clock management control |
0x4818 0528 | CM_DEFAULT_DMM_CLKCTRL | DMM clock management control |
0x4818 052C | CM_DEFAULT_FW_CLKCTRL | EMIF FW clock management control |
0x4818 0558 | CM_DEFAULT_USB_CLKCTRL | USB clock management control |
0x4818 0560 | CM_DEFAULT_SATA_CLKCTRL | SATA clock management control |
0x4818 0578 | CM_DEFAULT_PCI_CLKCTRL | PCI clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0600 | CM_IVAHD0_CLKSTCTRL | HDVICP2-0 clock domain power state transition |
0x4818 0620 | CM_IVAHD0_IVAHD_CLKCTRL | HDVICP2-0 clock management control |
0x4818 0624 | CM_IVAHD0_SL2_CLKCTRL | HDVICP2-0 SL2 clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0700 | CM_IVAHD1_CLKSTCTRL | HDVICP2-1 clock domain power state transition |
0x4818 0720 | CM_IVAHD1_IVAHD_CLKCTRL | HDVICP2-1 clock management control |
0x4818 0724 | CM_IVAHD1_SL2_CLKCTRL | HDVICP2-1 SL2 clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0800 | CM_IVAHD2_CLKSTCTRL | HDVICP2-2 clock domain power state transition |
0x4818 0820 | CM_IVAHD2_IVAHD_CLKCTRL | HDVICP2-2 clock management control |
0x4818 0824 | CM_IVAHD2_SL2_CLKCTRL | HDVICP2-2 SL2 clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0900 | CM_SGX_CLKSTCTRL | SGX530 clock domain power state transition |
0x4818 0920 | CM_SGX_SGX_CLKCTRL | SGX530 clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0A00 | PM_ACTIVE_PWRSTCTRL | Active power state control |
0x4818 0A04 | PM_ACTIVE_PWRSTST | Active power domain state status |
0x4818 0A10 | RM_ACTIVE_RSTCTRL | Active domain reset control release |
0x4818 0A14 | RM_ACTIVE_RSTST | Active domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0B00 | PM_DEFAULT_PWRSTCTRL | Default power state |
0x4818 0B04 | PM_DEFAULT_PWRSTST | Default power domain state 0 status |
0x4818 0B10 | RM_DEFAULT_RSTCTRL | Default subsystem reset control release |
0x4818 0B14 | RM_DEFAULT_RSTST | Default domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0C00 | PM_IVAHD0_PWRSTCTRL | HDVICP2-0 power state control |
0x4818 0C04 | PM_IVAHD0_PWRSTST | HDVICP2-0 power domain state status |
0x4818 0C10 | RM_IVAHD0_RSTCTRL | HDVICP2-0 subsystem reset control release |
0x4818 0C14 | RM_IVAHD0_RSTST | HDVICP2-0 domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0D00 | PM_IVAHD1_PWRSTCTRL | HDVICP2-1 power state control |
0x4818 0D04 | PM_IVAHD1_PWRSTST | HDVICP2-1 power domain state status |
0x4818 0D10 | RM_IVAHD1_RSTCTRL | HDVICP2-1 subsystem reset control release |
0x4818 0D14 | RM_IVAHD1_RSTST | HDVICP2-1 domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0E00 | PM_IVAHD2_PWRSTCTRL | HDVICP2-2 power state control |
0x4818 0E04 | PM_IVAHD2_PWRSTST | HDVICP2-2 power domain state status |
0x4818 0E10 | RM_IVAHD2_RSTCTRL | HDVICP2-2 subsystem reset control release |
0x4818 0E14 | RM_IVAHD2_RSTST | HDVICP2-2 domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 0F00 | PM_SGX_PWRSTCTRL | SGX530 power state control |
0x4818 0F04 | RM_SGX_RSTCTRL | SGX530 domain reset control release |
0x4818 0F10 | PM_SGX_PWRSTST | SGX530 power domain state status |
0x4818 0F14 | RM_SGX_RSTST | SGX530 domain reset source log |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 1400 | CM_ALWON_L3_SLOW_CLKSTCTRL | L3 clock domain power state transition |
0x4818 1404 | CM_ETHERNET_CLKSTCTRL | EMAC clock domain power state transition |
0x4818 1408 | CM_ALWON_L3_MED_CLKSTCTRL | L3 clock domain power state transition |
0x4818 140C | CM_MMU_CLKSTCTRL | MMU clock domain power state transition |
0x4818 1410 | CM_MMUCFG_CLKSTCTRL | MMU CFG clock domain power state transition |
0x4818 1414 | CM_ALWON_OCMC_0_CLKSTCTRL | OCMC 0 clock domain power state transition |
0x4818 1418 | CM_ALWON_OCMC_1_CLKSTCTRL | OCMC 1 clock domain power state transition |
0x4818 141C | CM_ALWON_MPU_CLKSTCTRL | Processor clock domain power state transition |
0x4818 1420 | CM_ALWON_SYSCLK4_CLKSTCTRL | SYSCLK4 clock domain power state transition |
0x4818 1424 | CM_ALWON_SYSCLK5_CLKSTCTRL | SYSCLK5 clock domain power state transition |
0x4818 1428 | CM_ALWON_SYSCLK6_CLKSTCTRL | SYSCLK6 clock domain power state transition |
0x4818 142C | CM_ALWON_RTC_CLKSTCTRL | RTC clock domain power state transition |
0x4818 1430 | CM_ALWON_L3_FAST_CLKSTCTRL | L3 clock domain power state transition |
0x4818 1540 | CM_ALWON_MCASP0_CLKCTRL | McASP 0 clock management control |
0x4818 1544 | CM_ALWON_MCASP1_CLKCTRL | McASP 1 clock management control |
0x4818 1548 | CM_ALWON_MCASP2_CLKCTRL | McASP 2 clock management control |
0x4818 154C | CM_ALWON_MCBSP_CLKCTRL | McBSP clock management control |
0x4818 1550 | CM_ALWON_UART_0_CLKCTRL | UART 0 clock management control |
0x4818 1554 | CM_ALWON_UART_1_CLKCTRL | UART 1 clock management control |
0x4818 1558 | CM_ALWON_UART_2_CLKCTRL | UART 2 clock management control |
0x4818 155C | CM_ALWON_GPIO_0_CLKCTRL | GPIO 0 clock management control |
0x4818 1560 | CM_ALWON_GPIO_1_CLKCTRL | GPIO 1 clock management control |
0x4818 1564 | CM_ALWON_I2C_0_CLKCTRL | I2C 0 clock management control |
0x4818 1568 | CM_ALWON_I2C_1_CLKCTRL | I2C 1 clock management control |
0x4818 1570 | CM_ALWON_TIMER_1_CLKCTRL | Timer1 clock management control |
0x4818 1574 | CM_ALWON_TIMER_2_CLKCTRL | Timer2 clock management control |
0x4818 1578 | CM_ALWON_TIMER_3_CLKCTRL | Timer3 clock management control |
0x4818 157C | CM_ALWON_TIMER_4_CLKCTRL | Timer4 clock management control |
0x4818 1580 | CM_ALWON_TIMER_5_CLKCTRL | Timer5 clock management control |
0x4818 1584 | CM_ALWON_TIMER_6_CLKCTRL | Timer6 clock management control |
0x4818 1588 | CM_ALWON_TIMER_7_CLKCTRL | Timer7 clock management control |
0x4818 158C | CM_ALWON_WDTIMER_CLKCTRL | WDTIMER clock management control |
0x4818 1590 | CM_ALWON_SPI_CLKCTRL | SPI clock management control |
0x4818 1594 | CM_ALWON_MAILBOX_CLKCTRL | MAILBOX clock management control |
0x4818 1598 | CM_ALWON_SPINBOX_CLKCTRL | SPINBOX clock management control |
0x4818 159C | CM_ALWON_MMUDATA_CLKCTRL | MMU DATA clock management control |
0x4818 15A8 | CM_ALWON_MMUCFG_CLKCTRL | MMU CFG clock management control |
0x4818 15B0 | CM_ALWON_SDIO_CLKCTRL | SDIO clock management control |
0x4818 15B4 | CM_ALWON_OCMC_0_CLKCTRL | OCMC 0 clock management control |
0x4818 15B8 | CM_ALWON_OCMC_1_CLKCTRL | OCMC 1 clock management control |
0x4818 15C4 | CM_ALWON_CONTROL_CLKCTRL | Control clock management control |
0x4818 15D0 | CM_ALWON_GPMC_CLKCTRL | GPMC clock management control |
0x4818 15D4 | CM_ALWON_ETHERNET_0_CLKCTRL | Ethernet 0 clock management control |
0x4818 15D8 | CM_ALWON_ETHERNET_1_CLKCTRL | Ethernet 1 clock management control |
0x4818 15DC | CM_ALWON_MPU_CLKCTRL | Processor clock management control |
0x4818 15E0 | CM_ALWON_DEBUGSS_CLKCTRL | Debug clock management control |
0x4818 15E4 | CM_ALWON_L3_CLKCTRL | L3 clock management control |
0x4818 15E8 | CM_ALWON_L4HS_CLKCTRL | L4 high-speed clock management control |
0x4818 15EC | CM_ALWON_L4LS_CLKCTRL | L4 standard-speed clock management control |
0x4818 15F0 | CM_ALWON_RTC_CLKCTRL | RTC clock management control |
0x4818 15F4 | CM_ALWON_TPCC_CLKCTRL | TPCC clock management control |
0x4818 15F8 | CM_ALWON_TPTC0_CLKCTRL | TPTC0 clock management control |
0x4818 15FC | CM_ALWON_TPTC1_CLKCTRL | TPTC1 clock management control |
0x4818 1600 | CM_ALWON_TPTC2_CLKCTRL | TPTC2 clock management control |
0x4818 1604 | CM_ALWON_TPTC3_CLKCTRL | TPTC3 clock management control |
0x4818 1608 | CM_ALWON_SR_0_CLKCTRL | SmartReflex 0 clock management control |
0x4818 160C | CM_ALWON_SR_1_CLKCTRL | SmartReflex 1 clock management control |
0x4818 1628 | CM_ALWON_CUST_EFUSE_CLKCTRL | Customer e-Fuse clock management control |
HEX ADDRESS | ACRONYM | REGISTER NAME |
---|---|---|
0x4818 1810 | RM_ALWON_RSTCTRL | ALWAYS ON domain resets control |
0x4818 1814 | RM_ALWON_RSTST | ALWAYS ON reset sources |
The SGX530 is a vector and 3D graphics accelerator for vector and 3-dimensional (3D) graphics applications. The SGX530 graphics accelerator efficiently processes a number of various multimedia data types concurrently:
This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.
The SGX530 has the following major features:
The device has multiple on-chip memories associated with its processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.
The device system memory mapping is broken into four 1-GB quadrants for target address spaces allocation. The four quadrants are labeled Q0, Q1, Q2 and Q3 for a total of 4-GB 32-bit address space. (HDVPSS includes a thirty-third address bit for an additional 4GB of address range; this is for virtual addressing and not physical memory addressing.) Inside each quadrant, system targets are mapped on 4-MB boundary (except EDMA targets which are decreased to 1-MB regions).
The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure. The NoC uses an internal packet-based protocol for forward (read command, write command with data payload) and backward (read response with data payload, write response) transactions. All exposed interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference standard.
Table 3-26 shows the general device level-3 (L3) memory map. The table represents the physical addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM, C674x DSP) may re-map these targets to different virtual addresses through an internal or external MMU. Processors without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all masters have access to all L3 regions, but only those with defined connectivity, as shown in Table 7-1. For a list of the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 7.2. The L3 interconnect returns an address-hole error if any initiator attempts to access a target to which it has no connection.
QUAD | BLOCK NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|---|
Q0 | GPMC | 0x0100 0000 | 0x1FFF FFFF | 496MB | GPMC(1) |
Q0 | PCIe Gen2 | 0x2000 0000 | 0x2FFF FFFF | 256MB | PCIe Gen2 Targets |
Q0 | Reserved | 0x3000 0000 | 0x3FFF FFFF | 256MB | Reserved |
Q1 | Reserved | 0x4000 0000 | 0x402F FFFF | 3MB | Reserved |
Q1 | L3 OCMC0 | 0x4030 0000 | 0x4033 FFFF | 256KB | OCMC SRAM |
Q1 | Reserved | 0x4034 0000 | 0x403F FFFF | 768KB | Reserved (OCMC RAM0) |
Q1 | L3 OCMC1 | 0x4040 0000 | 0x4043 FFFF | 256KB | OCMC SRAM |
Q1 | Reserved | 0x4044 0000 | 0x404F FFFF | 768KB | Reserved (OCMC RAM1) |
Q1 | Reserved | 0x4050 0000 | 0x407F FFFF | 3MB | Reserved |
Q1 | C674x | 0x4080 0000 | 0x4083 FFFF | 256KB | C674x UMAP0 (L2 RAM) |
Q1 | Reserved | 0x4084 0000 | 0x40DF FFFF | 5888KB | Reserved |
Q1 | C674x | 0x40E0 0000 | 0x40E0 7FFF | 32KB | C674x L1P Cache and RAM |
Q1 | Reserved | 0x40E0 8000 | 0x40EF FFFF | 992KB | Reserved |
Q1 | C674x | 0x40F0 0000 | 0x40F0 7FFF | 32KB | C674x L1D Cache and RAM |
Q1 | Reserved | 0x40F0 8000 | 0x40FF FFFF | 992KB | Reserved |
Q1 | Reserved | 0x4100 0000 | 0x41FF FFFF | 16MB | Reserved |
Q1 | Reserved | 0x4200 0000 | 0x43FF FFFF | 32MB | Reserved |
Q1 | L3 CFG Regs | 0x4400 0000 | 0x44BF FFFF | 12MB | L3 configuration registers |
Q1 | Reserved | 0x44C0 0000 | 0x45FF FFFF | 20MB | Reserved |
Q1 | McASP0 | 0x4600 0000 | 0x463F FFFF | 4MB | McASP0 DAT Port Access(2) |
Q1 | McASP1 | 0x4640 0000 | 0x467F FFFF | 4MB | McASP1 DAT Port Access(2) |
Q1 | McASP2 | 0x4680 0000 | 0x46BF FFFF | 4MB | McASP2 DAT Port Access(2) |
Q1 | HDMI 1.3 Tx | 0x46C0 0000 | 0x46FF FFFF | 4MB | HDMI 1.3 Tx |
Q1 | McBSP | 0x4700 0000 | 0x473F FFFF | 4MB | McBSP |
Q1 | USB2.0 | 0x4740 0000 | 0x477F FFFF | 4MB | USB2.0 Registers and CPPI |
Q1 | Reserved | 0x4780 0000 | 0x47BF FFFF | 4MB | Reserved |
Q1 | Reserved | 0x47C0 0000 | 0x47FF FFFF | 4MB | Reserved |
Q1 | L4 Standard domain | 0x4800 0000 | 0x48FF FFFF | 16MB | Standard Peripheral domain (see notes-list-normal) |
Q1 | EDMA TPCC | 0x4900 0000 | 0x490F FFFF | 1MB | EDMA TPCC Registers |
Q1 | Reserved | 0x4910 0000 | 0x497F FFFF | 7MB | Reserved |
Q1 | EDMA TPTC0 | 0x4980 0000 | 0x498F FFFF | 1MB | EDMA TPTC0 Registers |
Q1 | EDMA TPTC1 | 0x4990 0000 | 0x499F FFFF | 1MB | EDMA TPTC1 Registers |
Q1 | EDMA TPTC2 | 0x49A0 0000 | 0x49AF FFFF | 1MB | EDMA TPTC2 Registers |
Q1 | EDMA TPTC3 | 0x49B0 0000 | 0x49BF FFFF | 1MB | EDMA TPTC3 Registers |
Q1 | Reserved | 0x49C0 0000 | 0x49FF FFFF | 4MB | Reserved |
Q1 | L4 High-Speed Domain | 0x4A00 0000 | 0x4AFF FFFF | 16MB | High-Speed Peripheral domain (see notes-list-normal) |
Q1 | Instrumentation | 0x4B00 0000 | 0x4BFF FFFF | 16MB | EMU Subsystem region |
Q1 | DDR EMIF0 registers(3) | 0x4C00 0000 | 0x4CFF FFFF | 16MB | Configuration registers |
Q1 | DDR EMIF1 registers(3) | 0x4D00 0000 | 0x4DFF FFFF | 16MB | Configuration registers |
Q1 | DDR DMM Registers(3) | 0x4E00 0000 | 0x4FFF FFFF | 32MB | Configuration registers |
Q1 | GPMC Registers | 0x5000 0000 | 0x50FF FFFF | 16MB | Configuration registers |
Q1 | PCIe Gen2 Registers | 0x5100 0000 | 0x51FF FFFF | 16MB | Configuration registers |
Q1 | Reserved | 0x5200 0000 | 0x52FF FFFF | 16MB | Reserved |
Q1 | HDVICP2-2 Config | 0x5300 0000 | 0x53FF FFFF | 16MB | HDVICP2-2 Host Port |
Q1 | HDVICP2-2 SL2 | 0x5400 0000 | 0x54FF FFFF | 16MB | HDVICP2-2 SL2 Port |
Q1 | Reserved | 0x5500 0000 | 0x55FF FFFF | 16MB | Reserved |
Q1 | SGX530
(DM8168 only) |
0x5600 0000 | 0x56FF FFFF | 16MB | SGX530 Slave Port |
Q1 | Reserved
(DM8167 and DM8165 only) |
0x5600 0000 | 0x56FF FFFF | 16MB | Reserved |
Q1 | Reserved | 0x5700 0000 | 0x57FF FFFF | 16MB | Reserved |
Q1 | HDVICP2-0 Config | 0x5800 0000 | 0x58FF FFFF | 16MB | HDVICP2-0 Host Port |
Q1 | HDVICP2-0 SL2 | 0x5900 0000 | 0x59FF FFFF | 16MB | HDVICP2-0 SL2 Port |
Q1 | HDVICP2-1 Config | 0x5A00 0000 | 0x5AFF FFFF | 16MB | HDVICP2-1 Host Port |
Q1 | HDVICP2-1 SL2 | 0x5B00 0000 | 0x5BFF FFFF | 16MB | HDVICP2-1 SL2 Port |
Q1 | Reserved | 0x5C00 0000 | 0x5DFF FFFF | 32MB | Reserved |
Q1 | Reserved | 0x5E00 0000 | 0x5FFF FFFF | 32MB | Reserved |
Q1 | Tiler | 0x6000 0000 | 0x7FFF FFFF | 512MB | Virtual Tiled Address Space |
Q2 | DDR EMIF0 and EMIF1 SDRAM(4) | 0x8000 0000 | 0xBFFF FFFF | 1GB | DDR |
Q3 | DDR EMIF0 and EMIF1 SDRAM(4) | 0xC000 0000 | 0xFFFF FFFF | 1GB | DDR |
Q4-7 | DDR DMM | 0x1 0000 0000 | 0x1 FFFF FFFF | 4GB | DDR DMM Tiler Extended address map – Virtual Views (HDVPSS only) |
The L4 standard peripheral bus accesses standard peripherals and IP configuration registers. The memory map is shown in Table 3-27.
DEVICE NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|
L4 Standard Configuration | 0x4800 0000 | 0x4800 07FF | 2KB | Address and Protection (AP) |
0x4800 0800 | 0x4800 0FFF | 2KB | Link Agent (LA) | |
0x4800 1000 | 0x4800 13FF | 1KB | Initiator Port (IP0) | |
0x4800 1400 | 0x4800 17FF | 1KB | Initiator Port (IP1) | |
0x4800 1800 | 0x4800 1FFF | 2KB | Reserved (IP2 – IP3) | |
Reserved | 0x4800 2000 | 0x4800 7FFF | 24KB | Reserved |
e-Fuse Controller | 0x4800 8000 | 0x4800 8FFF | 4KB | Peripheral Registers |
0x4800 9000 | 0x4800 9FFF | 4KB | Support Registers | |
Reserved | 0x4800 A000 | 0x4800 FFFF | 24KB | Reserved |
System MMU | 0x4801 0000 | 0x4801 0FFF | 4KB | Peripheral Registers |
0x4801 1000 | 0x4801 1FFF | 4KB | Support Registers | |
Reserved | 0x4801 2000 | 0x4801 FFFF | 56KB | Reserved |
UART0 | 0x4802 0000 | 0x4802 0FFF | 4KB | Peripheral Registers |
0x4802 1000 | 0x4802 1FFF | 4KB | Support Registers | |
UART1 | 0x4802 2000 | 0x4802 2FFF | 4KB | Peripheral Registers |
0x4802 3000 | 0x4802 3FFF | 4KB | Support Registers | |
UART2 | 0x4802 4000 | 0x4802 4FFF | 4KB | Peripheral Registers |
0x4802 5000 | 0x4802 5FFF | 4KB | Support Registers | |
Reserved | 0x4802 6000 | 0x4802 7FFF | 8KB | Reserved |
I2C0 | 0x4802 8000 | 0x4802 8FFF | 4KB | Peripheral Registers |
0x4802 9000 | 0x4802 9FFF | 4KB | Support Registers | |
I2C1 | 0x4802 A000 | 0x4802 AFFF | 4KB | Peripheral Registers |
0x4802 B000 | 0x4802 BFFF | 4KB | Support Registers | |
Reserved | 0x4802 C000 | 0x4802 DFFF | 8KB | Reserved |
TIMER1 | 0x4802 E000 | 0x4802 EFFF | 4KB | Peripheral Registers |
0x4802 F000 | 0x4802 FFFF | 4KB | Support Registers | |
SPIOCP | 0x4803 0000 | 0x4803 0FFF | 4KB | Peripheral Registers |
0x4803 1000 | 0x4803 1FFF | 4KB | Support Registers | |
GPIO0 | 0x4803 2000 | 0x4803 2FFF | 4KB | Peripheral Registers |
0x4803 3000 | 0x4803 3FFF | 4KB | Support Registers | |
Reserved | 0x4803 4000 | 0x4803 7FFF | 16KB | Reserved |
McASP0 CFG | 0x4803 8000 | 0x4803 9FFF | 8KB | Peripheral Registers |
0x4803 A000 | 0x4803 AFFF | 4KB | Support Registers | |
Reserved | 0x4803 B000 | 0x4803 BFFF | 4KB | Reserved |
McASP1 CFG | 0x4803 C000 | 0x4803 DFFF | 8KB | Peripheral Registers |
0x4803 E000 | 0x4803 EFFF | 4KB | Support Registers | |
Reserved | 0x4803 F000 | 0x4803 FFFF | 4KB | Reserved |
TIMER2 | 0x4804 0000 | 0x4804 0FFF | 4KB | Peripheral Registers |
0x4804 1000 | 0x4804 1FFF | 4KB | Support Registers | |
TIMER3 | 0x4804 2000 | 0x4804 2FFF | 4KB | Peripheral Registers |
0x4804 3000 | 0x4804 3FFF | 4KB | Support Registers | |
TIMER4 | 0x4804 4000 | 0x4804 4FFF | 4KB | Peripheral Registers |
0x4804 5000 | 0x4804 5FFF | 4KB | Support Registers | |
TIMER5 | 0x4804 6000 | 0x4804 6FFF | 4KB | Peripheral Registers |
0x4804 7000 | 0x4804 7FFF | 4KB | Support Registers | |
TIMER6 | 0x4804 8000 | 0x4804 8FFF | 4KB | Peripheral Registers |
0x4804 9000 | 0x4804 9FFF | 4KB | Support Registers | |
TIMER7 | 0x4804 A000 | 0x4804 AFFF | 4KB | Peripheral Registers |
0x4804 B000 | 0x4804 BFFF | 4KB | Support Registers | |
GPIO1 | 0x4804 C000 | 0x4804 CFFF | 4KB | Peripheral Registers |
0x4804 D000 | 0x4804 DFFF | 4KB | Support Registers | |
Reserved | 0x4804 E000 | 0x4804 FFFF | 8KB | Reserved |
McASP2 CFG | 0x4805 0000 | 0x4805 1FFF | 8KB | Peripheral Registers |
0x4805 2000 | 0x4805 2FFF | 4KB | Support Registers | |
Reserved | 0x4805 3000 | 0x4805 FFFF | 52KB | Reserved |
SD and SDIO | 0x4806 0000 | 0x4806 FFFF | 64KB | Registers |
0x4807 0000 | 0x4807 0FFF | 4KB | Support Registers | |
Reserved | 0x4807 1000 | 0x4807 FFFF | 60KB | Reserved |
ELM | 0x4808 0000 | 0x4808 FFFF | 64KB | Error Location Module |
0x4809 0000 | 0x4809 0FFF | 4KB | Support Registers | |
Reserved | 0x4809 1000 | 0x480B FFFF | 188KB | Reserved |
RTC | 0x480C 0000 | 0x480C 0FFF | 4KB | Peripheral Registers |
0x480C 1000 | 0x480C 1FFF | 4KB | Support Registers | |
WDT1 | 0x480C 2000 | 0x480C 2FFF | 4KB | Peripheral Registers |
0x480C 3000 | 0x480C 3FFF | 4KB | Support Registers | |
Reserved | 0x480C 4000 | 0x480C 7FFF | 16KB | Reserved |
Mailbox | 0x480C 8000 | 0x480C 8FFF | 4KB | Peripheral Registers |
0x480C 9000 | 0x480C 9FFF | 4KB | Support Registers | |
Spinlock | 0x480C A000 | 0x480C AFFF | 4KB | Peripheral Registers |
0x480C B000 | 0x480C BFFF | 4KB | Support Registers | |
Reserved | 0x480C C000 | 0x480F FFFF | 208KB | Reserved |
HDVPSS | 0x4810 0000 | 0x4811 FFFF | 128KB | Peripheral Registers |
0x4812 0000 | 0x4812 0FFF | 4KB | Support Registers | |
Reserved | 0x4812 1000 | 0x4812 1FFF | 4KB | Reserved |
HDMI 1.3 Tx | 0x4812 2000 | 0x4812 2FFF | 4KB | Peripheral Registers |
0x4812 3000 | 0x4812 3FFF | 4KB | Support Registers | |
Reserved | 0x4812 4000 | 0x4813 FFFF | 112KB | Reserved |
Control Module | 0x4814 0000 | 0x4815 FFFF | 128KB | Peripheral Registers |
0x4816 0000 | 0x4816 0FFF | 4KB | Support Registers | |
Reserved | 0x4816 1000 | 0x4817 FFFF | 124KB | Reserved |
PRCM | 0x4818 0000 | 0x4818 2FFF | 12KB | Peripheral Registers |
0x4818 3000 | 0x4818 3FFF | 4KB | Support Registers | |
Reserved | 0x4818 4000 | 0x4818 7FFF | 16KB | Reserved |
SmartReflex0 | 0x4818 8000 | 0x4818 8FFF | 4KB | Peripheral Registers |
0x4818 9000 | 0x4818 9FFF | 4KB | Support Registers | |
SmartReflex1 | 0x4818 A000 | 0x4818 AFFF | 4KB | Peripheral Registers |
0x4818 B000 | 0x4818 BFFF | 4KB | Support Registers | |
OCP Watchpoint | 0x4818 C000 | 0x4818 CFFF | 4KB | Peripheral Registers |
0x4818 D000 | 0x4818 DFFF | 4KB | Support Registers | |
Reserved | 0x4818 E000 | 0x4818 EFFF | 4KB | Reserved |
0x4818 F000 | 0x4818 FFFF | 4KB | Reserved | |
Reserved | 0x4819 0000 | 0x4819 0FFF | 4KB | Reserved |
0x4819 1000 | 0x4819 1FFF | 4KB | Reserved | |
Reserved | 0x4819 2000 | 0x4819 2FFF | 4KB | Reserved |
0x4819 3000 | 0x4819 3FFF | 4KB | Reserved | |
Reserved | 0x4819 4000 | 0x4819 4FFF | 4KB | Reserved |
0x4819 5000 | 0x4819 5FFF | 4KB | Reserved | |
Reserved | 0x4819 6000 | 0x4819 6FFF | 4KB | Reserved |
0x4819 7000 | 0x4819 7FFF | 4KB | Reserved | |
DDR0 Phy Ctrl Regs | 0x4819 8000 | 0x4819 8FFF | 4KB | Peripheral Registers |
0x4819 9000 | 0x4819 9FFF | 4KB | Support Registers | |
DDR1 Phy Ctrl Regs | 0x4819 A000 | 0x4819 AFFF | 4KB | Peripheral Registers |
0x4819 B000 | 0x4819 BFFF | 4KB | Support Registers | |
Reserved | 0x4819 C000 | 0x481F FFFF | 400KB | Reserved |
Interrupt controller(1) | 0x4820 0000 | 0x4820 0FFF | 4KB | Cortex™-A8 Accessible Only |
Reserved(1) | 0x4820 1000 | 0x4823 FFFF | 252KB | Cortex™-A8 Accessible Only |
MPUSS config register(1) | 0x4824 0000 | 0x4824 0FFF | 4KB | Cortex™-A8 Accessible Only |
Reserved(1) | 0x4824 1000 | 0x4827 FFFF | 252KB | Cortex™-A8 Accessible Only |
Reserved(1) | 0x4828 1000 | 0x482F FFFF | 508KB | Cortex™-A8 Accessible Only |
Reserved | 0x4830 0000 | 0x48FF FFFF | 13MB | Reserved |
The L4 high-speed peripheral bus accesses the IP configuration registers of high-speed peripherals in L3. The memory map is shown in Table 3-28.
DEVICE NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|
L4 High Speed configuration | 0x4A00 0000 | 0x4A00 07FF | 2KB | Address and Protection (AP) |
0x4A00 0800 | 0x4A00 0FFF | 2KB | Link Agent (LA) | |
0x4A00 1000 | 0x4A00 13FF | 1KB | Initiator Port (IP0) | |
0x4A00 1400 | 0x4A00 17FF | 1KB | Initiator Port (IP1) | |
0x4A00 1800 | 0x4A00 1FFF | 2KB | Reserved (IP2 – IP3) | |
Reserved | 0x4A00 2000 | 0x4A07 FFFF | 504KB | Reserved |
Reserved | 0x4A08 0000 | 0x4A0A 0FFF | 132KB | Reserved |
Reserved | 0x4A0A 1000 | 0x4A0F FFFF | 380KB | Reserved |
EMAC0 | 0x4A10 0000 | 0x4A10 3FFF | 16KB | Peripheral Registers |
0x4A10 4000 | 0x4A10 4FFF | 4KB | Support Registers | |
Reserved | 0x4A10 5000 | 0x4A11 FFFF | 108KB | Reserved |
EMAC1 | 0x4A12 0000 | 0x4A12 3FFF | 16KB | Peripheral Registers |
0x4A12 4000 | 0x4A12 4FFF | 4KB | Support Registers | |
Reserved | 0x4A12 5000 | 0x4A13 FFFF | 108KB | Reserved |
SATA | 0x4A14 0000 | 0x4A14 FFFF | 64KB | Peripheral Registers |
0x4A15 0000 | 0x4A15 0FFF | 4KB | Support Registers | |
Reserved | 0x4A15 1000 | 0x4A17 FFFF | 188KB | Reserved |
Reserved | 0x4A18 0000 | 0x4A19 FFFF | 128KB | Reserved |
0x4A1A 0000 | 0x4A1A 0FFF | 4KB | Reserved | |
Reserved | 0x4A1A 1000 | 0x4AFF FFFF | 14716KB | Reserved |
The Tiling and Isometric Lightweight Engines for Rotation (TILER) ports are mainly used for optimized 2-D block accesses. The TILER also supports rotation of the image buffer at 0º, 90º, 180º, and 270º, with vertical and horizontal mirroring.
The TILER includes an additional 4-GB addressing range to access the frame buffer in these rotated and mirrored views. This range requires a thirty-third bit of address and is only accessible to peripherals that require access to the multiple views. On the device, this is limited to the HD Video Processing Subsystem (HDVPSS). (Other peripherals, based on ConnID, may access any one single view through the 512-MB TILER window region located in the base 4-GB range.)
The HDVPSS may use the virtual address space of 4GB (0x1:0000:0000 – 0x1:FFFF:FFFF) since various VPDMA clients of the HDVPSS may need to simultaneously access multiple 2-D images with different orientations of the image buffers.
The top 4-GB address space is divided into eight sections of 512MB each. These eight sections correspond to the eight different orientations as shown in Table 3-29.
BLOCK NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|
Tiler View 0 | 0x1 0000 0000 | 0x1 1FFF FFFF | 512MB | Natural 0° View |
Tiler View 1 | 0x1 2000 0000 | 0x1 3FFF FFFF | 512MB | 0° with Vertical Mirror View |
Tiler View 2 | 0x1 4000 0000 | 0x1 5FFF FFFF | 512MB | 0° with Horizontal Mirror View |
Tiler View 3 | 0x1 6000 0000 | 0x1 7FFF FFFF | 512MB | 180° View |
Tiler View 4 | 0x1 8000 0000 | 0x1 9FFF FFFF | 512MB | 90° with Vertical Mirror View |
Tiler View 5 | 0x1 A000 0000 | 0x1 BFFF FFFF | 512MB | 270° View |
Tiler View 6 | 0x1 C000 0000 | 0x1 DFFF FFFF | 512MB | 90° View |
Tiler View 7 | 0x1 E000 0000 | 0x1 FFFF FFFF | 512MB | 90° with Horizontal Mirror View |
The Cortex™-A8 includes an memory management unit (MMU) to translate virtual addresses to physical addresses which are then decoded within the Host ARM Subsystem. The subsystem includes its own ROM and RAM, as well as configuration registers for its interrupt controller. These addresses are hard-coded within the subsystem. In addition, the upper 2GB of address space is routed to a special port (Master 0) intended for low-latency access to DDR memory. All other physical addresses are routed to the L3 port (Master 1) where they are decoded by the device infrastructure. The Cortex™-A8 memory map is shown in Table 3-30.
REGION NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|
Boot Space | 0x0000 0000 | 0x000F FFFF | 1MB | Boot Space |
L3 Target Space | 0x0000 0000 | 0x1FFF FFFF | 512MB | GPMC |
0x2000 0000 | 0x2FFF FFFF | 256MB | PCIe Gen2 Targets | |
0x3000 0000 | 0x3FFF FFFF | 256MB | Reserved | |
ROM internal(1) | 0x4000 0000 | 0x4001 FFFF | 128KB | Reserved |
0x4002 0000 | 0x4002 BFFF | 48KB | Public | |
0x4002 C000 | 0x400F FFFF | 848KB | Reserved | |
Reserved(1) | 0x4010 0000 | 0x401F FFFF | 1MB | Reserved |
Reserved(1) | 0x4020 0000 | 0x402E FFFF | 960KB | Reserved |
Reserved | 0x402F 0000 | 0x402F FFFF | 64KB | Reserved |
L3 Target Space | 0x4030 0000 | 0x4033 FFFF | 256KB | OCMC SRAM |
0x4034 0000 | 0x403F FFFF | 768KB | Reserved | |
0x4040 0000 | 0x4043 FFFF | 256KB | OCMC SRAM | |
0x4044 0000 | 0x404F FFFF | 768KB | Reserved | |
0x4050 0000 | 0x407F FFFF | 3MB | Reserved | |
0x4080 0000 | 0x4083 FFFF | 256KB | C674x UMAP0 (L2 RAM) | |
0x4084 0000 | 0x40DF FFFF | 5888KB | Reserved | |
0x40E0 0000 | 0x40E0 7FFF | 32KB | C674x L1P Cache and RAM | |
0x40E0 8000 | 0x40EF FFFF | 992KB | Reserved | |
0x40F0 0000 | 0x40F0 7FFF | 32KB | C674x L1D Cache and RAM | |
0x40F0 8000 | 0x40FF FFFF | 992KB | Reserved | |
0x4100 0000 | 0x41FF FFFF | 16MB | Reserved | |
0x4200 0000 | 0x43FF FFFF | 32MB | Reserved | |
0x4400 0000 | 0x44BF FFFF | 12MB | L3 configuration registers | |
0x44C0 0000 | 0x45FF FFFF | 20MB | Reserved | |
0x4600 0000 | 0x463F FFFF | 4MB | McASP0 | |
0x4640 0000 | 0x467F FFFF | 4MB | McASP1 | |
0x4680 0000 | 0x46BF FFFF | 4MB | McASP2 | |
0x46C0 0000 | 0x46FF FFFF | 4MB | HDMI 1.3 Tx | |
0x4700 0000 | 0x473F FFFF | 4MB | McBSP | |
0x4740 0000 | 0x477F FFFF | 4MB | USB2.0 Registers and CPPI | |
0x4780 0000 | 0x47BF FFFF | 4MB | Reserved | |
0x47C0 0000 | 0x47FF FFFF | 4MB | Reserved | |
0x4800 0000 | 0x481F FFFF | 2MB | Standard Peripheral domain (see Table 3-27) | |
ARM Subsystem INTC(1) | 0x4820 0000 | 0x4820 0FFF | 4KB | Cortex™-A8 Interrupt Controller |
Reserved(1) | 0x4820 1000 | 0x4823 FFFF | 252KB | Reserved |
Reserved(1) | 0x4824 1000 | 0x4827 FFFF | 252KB | Reserved |
L3 Target Space | 0x4830 0000 | 0x48FF FFFF | 13MB | Standard Peripheral domain (see Table 3-27) |
0x4900 0000 | 0x490F FFFF | 1MB | EDMA TPCC Registers | |
0x4910 0000 | 0x497F FFFF | 7MB | Reserved | |
0x4980 0000 | 0x498F FFFF | 1MB | EDMA TPTC0 Registers | |
0x4990 0000 | 0x499F FFFF | 1MB | EDMA TPTC1 Registers | |
0x49A0 0000 | 0x49AF FFFF | 1MB | EDMA TPTC2 Registers | |
0x49B0 0000 | 0x49BF FFFF | 1MB | EDMA TPTC3 Registers | |
0x49C0 0000 | 0x49FF FFFF | 4MB | Reserved | |
0x4A00 0000 | 0x4AFF FFFF | 16MB | High Speed Peripheral domain (see Table 3-28) | |
0x4B00 0000 | 0x4BFF FFFF | 16MB | EMU Subsystem region | |
0x4C00 0000 | 0x4CFF FFFF | 16MB | DDR EMIF0(2) Configuration registers | |
0x4D00 0000 | 0x4DFF FFFF | 16MB | DDR EMIF1(2) Configuration registers | |
0x4E00 0000 | 0x4FFF FFFF | 32MB | DDR DMM(2) Configuration registers | |
0x5000 0000 | 0x50FF FFFF | 16MB | GPMC Configuration registers | |
0x5100 0000 | 0x51FF FFFF | 16MB | PCIE Configuration registers | |
0x5200 0000 | 0x52FF FFFF | 16MB | Reserved | |
0x5300 0000 | 0x53FF FFFF | 16MB | HDVICP2-2 Host Port | |
0x5400 0000 | 0x54FF FFFF | 16MB | HDVICP2-2 SL2 Port | |
0x5500 0000 | 0x55FF FFFF | 16MB | Reserved | |
0x5600 0000 | 0x56FF FFFF | 16MB | SGX530 Slave Port
(DM8168 only) |
|
0x5600 0000 | 0x56FF FFFF | 16MB | Reserved
(DM8167 and DM8165 only) |
|
0x5700 0000 | 0x57FF FFFF | 16MB | Reserved | |
0x5800 0000 | 0x58FF FFFF | 16MB | HDVICP2-0 Host Port | |
0x5900 0000 | 0x59FF FFFF | 16MB | HDVICP2-0 SL2 Port | |
0x5A00 0000 | 0x5AFF FFFF | 16MB | HDVICP2-1 Host Port | |
0x5B00 0000 | 0x5BFF FFFF | 16MB | HDVICP2-1 SL2 Port | |
0x5C00 0000 | 0x5FFF FFFF | 64MB | Reserved | |
0x6000 0000 | 0x7FFF FFFF | 512MB | TILER Window | |
DDR EMIF0 and EMIF1 SDRAM(3)(4) | 0x8000 0000 | 0xBFFF FFFF | 1GB | DDR |
DDR EMIF0 and EMIF1 SDRAM(3)(4) | 0xC000 0000 | 0xFFFF FFFF | 1GB | DDR |
Because the C674x DSP has specific hardwired address decoding built in, the C674x memory map is slightly different than that of the Cortex™-A8. The C674x has a separate CFG bus which is used to access L4 peripherals and its UMAP1 bus has a direct connection into HDVICP2 SL2 (HDVICP2-0 and HDVICP2-1 only) memories. All C674x MDMA port accesses are routed through the System MMU for address translation.
REGION NAME | START ADDRESS (HEX) | END ADDRESS (HEX) | SIZE | DESCRIPTION |
---|---|---|---|---|
Reserved(1) | 0x0000 0000 | 0x003F FFFF | 4MB | Reserved |
UMAP1(1) | 0x0040 0000 | 0x0043 FFFF | 256KB | C674x UMAP1 (HDVICP2-0 SL2) |
Reserved (UMAP1)(1) | 0x0044 0000 | 0x004F FFFF | 768KB | Reserved |
UMAP1(1) | 0x0050 0000 | 0x0053 FFFF | 256KB | C674x UMAP1 (HDVICP2-1 SL2) |
Reserved (UMAP1)(1) | 0x0054 0000 | 0x005F FFFF | 768KB | Reserved |
Reserved(1) | 0x0060 0000 | 0x007F FFFF | 2MB | Reserved |
L2 SRAM(1) | 0x0080 0000 | 0x0083 FFFF | 256KB | C674x UMAP0 (L2 RAM) |
Reserved(1) | 0x0084 0000 | 0x00DF FFFF | 5888KB | Reserved |
L1P SRAM(1) | 0x00E0 0000 | 0x00E0 7FFF | 32KB | C674x L1P Cache and RAM |
Reserved(1) | 0x00E0 8000 | 0x00EF FFFF | 992KB | Reserved |
L1D SRAM(1) | 0x00F0 0000 | 0x00F0 7FFF | 32KB | C674x L1D Cache and RAM |
Reserved(1) | 0x00F0 8000 | 0x017F FFFF | 9184KB | Reserved |
Internal CFG(2)(3) | 0x0180 0000 | 0x01BF FFFF | 4MB | C674x Internal CFG registers |
Reserved(3) | 0x01C0 0000 | 0x07FF FFFF | 100MB | Reserved |
L4 Standard Domain(3) | 0x0800 0000 | 0x08FF FFFF | 16MB | Peripheral Domain (see Table 3-27) |
EDMA TPCC(3) | 0x0900 0000 | 0x090F FFFF | 1MB | EDMA TPCC Registers |
Reserved(3) | 0x0910 0000 | 0x097F FFFF | 7MB | Reserved |
EDMA TPTC0(3) | 0x0980 0000 | 0x098F FFFF | 1MB | EDMA TPTC0 Registers |
EDMA TPTC1(3) | 0x0990 0000 | 0x099F FFFF | 1MB | EDMA TPTC1 Registers |
EDMA TPTC2(3) | 0x09A0 0000 | 0x09AF FFFF | 1MB | EDMA TPTC2 Registers |
EDMA TPTC3(3) | 0x09B0 0000 | 0x09BF FFFF | 1MB | EDMA TPTC3 Registers |
Reserved(3) | 0x09C0 0000 | 0x09FF FFFF | 4MB | Reserved |
L4 High-Speed Domain(3) | 0x0A00 0000 | 0x0AFF FFFF | 16MB | Peripheral Domain (see Table 3-28) |
Reserved(3) | 0x0B00 0000 | 0x0FFF FFFF | 80MB | Reserved |
C674x L1 and L2(4) | 0x1000 0000 | 0x10FF FFFF | 16MB | C674x Internal Global Address |
MDMA L3(5) | 0x1100 0000 | 0xFFFF FFFF | 3824MB | System MMU Mapped L3 Regions |