JAJSHI6G June 2018 – July 2021 TPS25830-Q1 , TPS25831-Q1
PRODUCTION DATA
The voltage on the EN/UVLO pin controls the ON or OFF operation of TPS2583x-Q1. An EN/UVLO pin voltage higher than VEN/UVLO-H is required to start the internal regulator and begin monitoring the CCn lines for a valid Type-C connection. The internal USB monitoring circuitry is on when VIN is within the operation range and the EN/UVLO threshold is cleared; however, the buck regulator does not begin operation until a valid USB Type-C detection has been made. This feature ensures the "cold socket" (0 V) USB Type-C VBUS requirement is met. The EN/UVLO pin is an input and cannot be left open or floating. The simplest way to enable the operation of the TPS2583x-Q1 is to connect the EN to VIN. This connection allows self-start-up of the TPS2583x-Q1 when VIN is within the operation range.
Many applications will benefit from the employment of an enable divider, RENT and RENB, (Figure 10-3) to establish a precision system UVLO level for the TPS2583x-Q1. The system UVLO can be used for sequencing, ensuring reliable operation, or supply protection, such as a battery discharge level. To ensure the USB port VBUS is within the 5-V operating range as required for USB compliance (for the latest USB specifications and requirements, refer to USB.org), TI suggests that the RENT and RENB resistors be chosen so that the TPS2583x-Q1 enables when VIN is approximately 6 V. Considering the drop out voltage of the buck regulator and IR loses in the system, 6 V provides adequate margin to maintain VBUS within USB specifications. If system requirements such as a warm crank (start) automotive scenario require operation with VIN < 6 V, the values of RENT and RENB can be calculated assuming a lower VIN. An external logic signal can also be used to drive EN/UVLO input when a microcontroller is present and it is desirable to enable or disable the USB port remotely for other reasons.
UVLO configuration using external resistors is governed by the following equations:
Example:
VIN(ON) = 6 V (user choice)
RENB = 5 kΩ (user choice)
RENT = [(VIN(ON) / VEN/UVLO_H) - 1] × RENB= 19.6 kΩ. Choose standard 20 kΩ.
Therefore VIN(OFF) = 6 V × [1 - (0.09 V / 1.2 V)] = 5.55 V
Figure 10-4 shows a typical start-up waveform, indicating typical timings when Rd connected to CC line. The rise time of DCDC VBUS voltage is about 5 ms.
For TPS25830-Q1, the pin voltage must meet the requirement below during 150 ms (typical) Rd assert deglitch time. See Figure 10-5:
After the TPS25830-Q1 Rd assert deglitch time, there is no additional requirement on these pins. In real application, LD_DET pin can be used to configure the timing sequence.