SLUSC40 Data sheet

SLUSC40B July 2016 – February 2017 TPS53667

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTA|40
- MPQF134A

サーマルパッド・メカニカル・データ

RTA|40
- QFND055H

発注情報

7 Detailed Description

7.1 Overview

The TPS53667 device is a DCAP+ mode adaptive on-time controller.

The output voltage is set using a DAC that outputs a reference in accordance with the 8-bit VID code defined in Table 1. In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in the TPS53667 device, the cycle begins when the current feedback reaches an error voltage level which corresponds to the amplified voltage difference between the DAC voltage and the feedback output voltage with droop. In the case of multi-phase operations, the current feedback from all the phases is summed, and is amplified using the ISUM pin to adjust the load-line. Also zero-load line operation can be easily configured with external resistor or internal NVM selection.

7.2 Functional Block Diagram

TPS53667 Block_Diagram_SLUSC40 - Copy.gif

7.3 Feature Description

7.3.1 V3R3 LDO

V3R3 is an LDO output generated from V5. It is used as internal digital circuit supply and 1-uF to 4.7-uF ceramic decoupling capacitor to GND pin is recommended.

When V5 exceeds V_V5UVLOH (4.25 V typically), V3R3 begins to ramp up. The startup time for V3R3 is approximately 600 µs as shown in Figure 7.

Figure 7. V3R3 Startup Waveform

After V3R3 has reached its operational level, the TPS53667 begins to initialize the internal circuit and reads the pinstrap configurations. This pinstrap reading completes in approximately 1.2 ms, and can communicate to the PMBus 1.5 ms after V3R3 powers up.

NOTE

This device does not require a high ENABLE signal in order for the V3R3 LDO to start up.

Use V3R3 as pull-up voltage for CSPx (to disable phases), ENABLE, VR_RDY, VR_HOT, and VR_FAULT. Because the V3R3 maximum current capability is approximately 5 mA, choose pull-up resistances carefully.

Directly tie CSP6,CSP5, CSP4, CSP3 or CSP2 to the V3R3 pin according to to disable the corresponding phase.

7.3.2 PWM Operation

As shown in the Functional Block Diagram, in 6-phase continuous conduction mode, the device operates as described in Figure 8.

Figure 8. D-CAP+ Mode Basic Waveforms

Starting with the condition that the high-side FETs are off and the low-side FETs are on, the summed current feedback (V_ISUM) is higher than the summed error amplifier output (V_COMP) and the internal ramp signal (V_RAMP). I_SUM falls until it hits V_COMP+V_RAMP, which contains a component of the output ripple voltage. The PWM comparator senses where the two waveforms cross and triggers the on-time generator. This generates the internal SW_CLK. Each SW_CLK corresponds to one switching ON pulse for one phase.

In case of single-phase operation, every SW_CLK generates a switching pulse on the same phase. Also, V_ISUM corresponds to just a single-phase inductor current.

In case of multi-phase operation, the SW_CLK gets distributed to each of the phases in a cycle. This approach of using the summed inductor current and cyclically distributing the ON pulses to each phase automatically gives the required interleaving of 360 / n, where n is the number of phases.

7.3.3 Current Sense and IMON Calculation

The TPS53667 device provides independent channels of current feedback for every phase to increase the system accuracy and reduce the dependence of circuit performance on layout compared to an externally summed architecture. The current sensing signals are from TI smart power stages (at 5mV/A) (ex: CSD9549x) and are already temperature-compensated. The pins CSP1, CSP2, CSP3, CSP4, CSP5, and CSP6 are used for the individual phases of the phase current sensing.

The sensed currents are then summed together and generate a current output to IMON pin. A resistor is connected to IMON pin to generate the V_IMON voltage.

Equation 1. TPS53667 q_vimon2_slusc39.gif

where

V_CSPx is the voltage of CSPx pin
n is the number of active phases
R_IMON is the value of resistor between the IMON pin and GND in kΩ

Then the V_IMON voltage translates to a digital IMON reading as shown in Equation 2.

Equation 2. TPS53667 q_imon_slusc39.gif

where

0.85 is the voltage correlated to I_MAX

When V_IMON is 0.85 V, the IMON reading should be equal to I_MAX.

The digital IMON then can be reported to the system by using PMBus command READ_IOUT.

7.3.4 Setting the Load-Line (DROOP)

Figure 9. Load Line

A resistor between the ISUM pin and the VREF pin sets the load line in non-zero load line mode.

Equation 3. TPS53667 q_vdroop_slusc39.gif

where

g_M(isum) is the gain of the internal I_SUM amplifier, (500 µS typical)
R_ISUM is the value of resistor between the ISUM pin and the VREF pin to adjust the load line
R_CS is the effective current sense resistance of TI smart power stages, (5 mΩ for CSD9549x)
I_OUT is the load current

A desired zero load-line can be implemented by putting a 0 Ω between ISUM and VREF pins or by shorting the ISUM and VREF pins directly.

7.3.5 Load Transitions

When there is a sudden load increase, the output voltage immediately drops. The TPS53667 device reacts to this drop in a rising voltage on the COMP pin. This rise forces the PWM pulses to come in sooner and more frequently which causes the inductor current to rapidly increase. As the inductor current reaches the new load current, the device reaches a steady-state operating condition and the PWM switching resumes the steady-state frequency.

When there is a sudden load release, the output voltage flies high. The TPS53667 device reacts to this rise in a falling voltage on the COMP pin. This drop forces the PWM pulses to be delayed until the inductor current reaches the new load current. At that point, the switching resumes and steady-state switching continues.

Please note in Figure 10 and Figure 11, the ripples on V_OUT, V_RAMP, and V_COMP voltages are not shown for simplicity.

Figure 10. Load Insertion

Figure 11. Load Release

7.3.6 Overshoot Reduction (OSR)

The problem of overshoot in low duty-cycle synchronous buck converters is well known, and results from the output inductor having a small voltage (V_OUT) with which to respond to a transient load release.

For simplicity, Figure 12 shows a single phase converter. In an ideal converter, with typical input voltage of 12 V and a 1.0-V output, the inductor has 11.0 V (12 V – 1.0 V) to respond to a transient load increase, but only 1.0 V to respond once the load releases.

Figure 12. Representative Schematic of Synchronous Buck Converter Circuit

With the Overshoot Reduction (OSR) feature enabled, when the summed voltage of V_OUT and V_DROOPexceeds the DAC voltage V_DAC by the OSR value specified in the Electrical Characteristics table, the PWM pulses immediately become tri-state to turn off both the high-side and low-side FETs. When the low-side FETs are turned OFF, the energy in the inductor is partially dissipated by the body diodes. Please note the ON pulse width can be also truncated immediately regardless of the load transient timing, and this feature can further reduce the overshoot when compared to the conventional constant on-time controllers as shown in Figure 13 .

Figure 13. Performance for a Load Transient Release with OSR Enabled

7.3.7 Undershoot Reduction (USR)

When the transient load increase becomes quite large, it becomes difficult to meet the energy demanded by the load especially at lower input voltages. Then it is necessary to quickly increase the energy in the inductors during the transient load increase. This is achieved in TPS53667 by enabling pulse overlapping. In order to maintain the interleaving of the multi-phase configuration and yet be able to have pulse-overlapping during load-insertion, the Undershoot Reduction (USR) mode is entered only when necessary. This mode is entered when the difference between DAC voltage and the summed voltage of V_OUT and V_DROOP exceeds the USR voltage level specified in the Electrical Characteristics table.

The waveforms in Figure 14 indicate the performance with USR. It can be seen that it is possible to eliminate undershoot by enabling USR. This allows reduced output capacitance to be used and still meets the specification.

When the transient condition is over, the interleaving of the phases is resumed.

Figure 14. Performance for a Load Transient Step-up With USR Enabled

7.3.8 AutoBalance™ Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of each phase to equalize the current in each phase as shown in Figure 15. The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. The V_IN voltage charges C_t(on) through R_t(on). The pulse terminates when the voltage at C_t(on) matches the on-time reference, which normally equals the DAC voltage (V_DAC).

The circuit operates in the following fashion. First assume that the 5-µs averaged value from each phase current are equal. In this case, the PWM modulator terminates at V_DAC, and the normal pulse width is delivered to the system. If instead, I1 > I_AVG, then an offset is subtracted from V_DAC, and the pulse width for Phase 1 is shortened to reduce the phase current in Phase 1 for balancing. If I1 < I_AVG, then a longer pulse is generated to increase the phase current in Phase 1 to achieve current balancing.

Figure 15. AutoBalance Current Sharing Circuit Detail

7.3.9 Phase Overlap

In TPS53667, phase overlap is allowed during both steady state and transient operation. The duty cycle is not limited to 1/n (where n is the phase number) unlike TPS53647

7.3.10 VID

The DAC voltage V_DAC can be changed according to Table 1.

The slew rate for a change is set by the resistor at SLEW-MODE pin, as defined in the Electrical Characteristics table.

Table 1. VID Table

VID Hex VALUE	VR12.0 VOLTAGE (V)	VR12.5 VOLTAGE (V)
00	0	0
01	0.25	0.50
02	0.255	0.51
03	0.26	0.52
04	0.265	0.53
05	0.27	0.54
06	0.275	0.55
07	0.28	0.56
08	0.285	0.57
09	0.29	0.58
0A	0.295	0.59
0B	0.30	0.60
0C	0.305	0.61
0D	0.31	0.62
0E	0.315	0.63
0F	0.32	0.64
10	0.325	0.65
11	0.33	0.66
12	0.335	0.67
13	0.34	0.68
14	0.345	0.69
15	0.35	0.70
16	0.355	0.71
17	0.36	0.72
18	0.365	0.73
19	0.37	0.74
1A	0.375	0.75
1B	0.38	0.76
1C	0.385	0.77
1D	0.39	0.78
1E	0.395	0.79
1F	0.40	0.80
20	0.405	0.81
21	0.41	0.82
22	0.415	0.83
23	0.42	0.84
24	0.425	0.85
25	0.43	0.86
26	0.435	0.87
27	0.44	0.88
28	0.445	0.89
29	0.45	0.90
2A	0.455	0.91
2B	0.46	0.92
2C	0.465	0.93
2D	0.47	0.94
2E	0.475	0.95
2F	0.48	0.96
30	0.485	0.97
31	0.49	0.98
32	0.495	0.99
33	0.50	1.00
34	0.505	1.01
35	0.51	1.02
36	0.515	1.03
37	0.52	1.04
38	0.525	1.05
39	0.53	1.06
3A	0.535	1.07
3B	0.54	1.08
3C	0.545	1.09
3D	0.55	1.10
3E	0.555	1.11
3F	0.56	1.12
40	0.565	1.13
41	0.57	1.14
42	0.575	1.15
43	0.58	1.16
44	0.585	1.17
45	0.59	1.18
46	0.595	1.19
47	0.60	1.20
48	0.605	1.21
49	0.61	1.22
4A	0.615	1.23
4B	0.62	1.24
4C	0.625	1.25
4D	0.63	1.26
4E	0.635	1.27
4F	0.64	1.28
50	0.645	1.29
51	0.65	1.30
52	0.655	1.31
53	0.66	1.32
54	0.665	1.33
55	0.67	1.34
56	0.675	1.35
57	0.68	1.36
58	0.685	1.37
59	0.69	1.38
5A	0.695	1.39
5B	0.70	1.40
5C	0.705	1.41
5D	0.71	1.42
5E	0.715	1.43
5F	0.72	1.44
60	0.725	1.45
61	0.73	1.46
62	0.735	1.47
63	0.74	1.48
64	0.745	1.49
65	0.75	1.50
66	0.755	1.51
67	0.76	1.52
68	0.765	1.53
69	0.77	1.54
6A	0.775	1.55
6B	0.78	1.56
6C	0.785	1.57
6D	0.79	1.58
6E	0.795	1.59
6F	0.80	1.60
70	0.805	1.61
71	0.81	1.62
72	0.815	1.63
73	0.82	1.64
74	0.825	1.65
75	0.83	1.66
76	0.835	1.67
77	0.84	1.68
78	0.845	1.69
79	0.85	1.70
7A	0.855	1.71
7B	0.86	1.72
7C	0.865	1.73
7D	0.87	1.74
7E	0.875	1.75
7F	0.88	1.76
80	0.885	1.77
81	0.89	1.78
82	0.895	1.79
83	0.90	1.80
84	0.905	1.81
85	0.91	1.82
86	0.915	1.83
87	0.92	1.84
88	0.925	1.85
89	0.93	1.86
8A	0.935	1.87
8B	0.94	1.88
8C	0.945	1.89
8D	0.95	1.90
8E	0.955	1.91
8F	0.96	1.92
90	0.965	1.93
91	0.97	1.94
92	0.975	1.95
93	0.98	1.96
94	0.985	1.97
95	0.99	1.98
96	0.995	1.99
97	1.00	2.00
98	1.005	2.01
99	1.01	2.02
9A	1.015	2.03
9B	1.02	2.04
9C	1.025	2.05
9D	1.03	2.06
9E	1.035	2.07
9F	1.04	2.08
A0	1.045	2.09
A1	1.05	2.10
A2	1.055	2.11
A3	1.06	2.12
A4	1.065	2.13
A5	1.07	2.14
A6	1.075	2.15
A7	1.08	2.16
A8	1.085	2.17
A9	1.09	2.18
AA	1.095	2.19
AB	1.10	2.20
AC	1.105	2.21
AD	1.11	2.22
AE	1.115	2.23
AF	1.12	2.24
B0	1.125	2.25
B1	1.13	2.26
B2	1.135	2.27
B3	1.14	2.28
B4	1.145	2.29
B5	1.15	2.30
B6	1.155	2.31
B7	1.16	2.32
B8	1.165	2.33
B9	1.17	2.34
BA	1.175	2.35
BB	1.18	2.36
BC	1.185	2.37
BD	1.19	2.38
BE	1.195	2.39
BF	1.20	2.40
C0	1.205	2.41
C1	1.21	2.42
C2	1.215	2.43
C3	1.22	2.44
C4	1.225	2.45
C5	1.23	2.46
C6	1.235	2.47
C7	1.24	2.48
C8	1.245	2.49
C9	1.25	2.50
CA	1.255	n/a
CB	1.26	n/a
CC	1.265	n/a
CD	1.27	n/a
CE	1.275	n/a
CF	1.28	n/a
D0	1.285	n/a
D1	1.29	n/a
D2	1.295	n/a
D3	1.30	n/a
D4	1.305	n/a
D5	1.31	n/a
D6	1.315	n/a
D7	1.32	n/a
D8	1.325	n/a
D9	1.33	n/a
DA	1.335	n/a
DB	1.34	n/a
DC	1.345	n/a
DD	1.35	n/a
DE	1.355	n/a
DF	1.36	n/a
E0	1.365	n/a
E1	1.37	n/a
E2	1.375	n/a
E3	1.38	n/a
E4	1.385	n/a
E5	1.39	n/a
E6	1.395	n/a
E7	1.40	n/a
E8	1.405	n/a
E9	1.41	n/a
EA	1.415	n/a
EB	1.42	n/a
EC	1.425	n/a
ED	1.43	n/a
EE	1.435	n/a
EF	1.44	n/a
F0	1.445	n/a
F1	1.45	n/a
F2	1.455	n/a
F3	1.46	n/a
F4	1.465	n/a
F5	1.47	n/a
F6	1.475	n/a
F7	1.48	n/a
F8	1.485	n/a
F9	1.49	n/a
FA	1.495	n/a
FB	1.50	n/a
FC	1.505	n/a
FD	1.51	n/a
FE	1.515	n/a
FF	1.52	n/a

7.3.11 PWM and SKIP Signals

The PWM and SKIP-NVM signals are output from the controller to drive the TI smart power stages. Both signals are 3.3-V logic based. The PWM signal is logic high to turn on the high-side MOSFET and logic low to turn on the low-side MOSFET. When both high-side and low-side MOSFETs are expected to be OFF, the PWM signal is driven to tri-state condition (1.7 V). The SKIP-NVM pin is asserted low during the soft-start period.

7.3.12 TSEN (Thermal Sense) Pin

TI smart power stage (ex: CSD9549x) senses the die temperature and sends out the temperature information as a voltage through the TAO pin. In a multi-phase application, the TAO pin of the TI smart power stages are connected and then tied to the TSEN pin of the TPS53667 device. In this case, the device reports the temperature of the hottest power stage. The reported temperature can be calculated as shown in Equation 4.

Equation 4. TPS53667 q_temp_slusc39.gif

where

TEMP is the sensed temperature in °C
V_TSEN is the voltage at TSEN pin

NOTE

The maximum temperature that can be sensed is 127.9 °C. If the TSEN voltage (V_TSEN) is higher than the voltage associated to 127.9 °C, the device continues to report 127.9 °C.

TSEN signal is also used as an indicator for power stage fault. When an internal fault occurs in the TI smart power stage (CSD9549x), the power stage pulls the TAO pin high. In the default configuration, if the TSEN voltage is higher than 2.5 V, the TPS53667 device senses the fault and turns off both the high-side and the low-side MOSFETS. There is also an option to disable power stage fault as described in MFR_SPECIFIC_07[3].

Figure 16. Temperature Sense

7.3.13 RESET Function

During adaptive voltage scaling (AVS) operation, the voltage may become falsely adjusted to be out of ASIC operating range. The RESET function returns the voltage to the VBOOT voltage. When the voltage is out of ASIC operating range, the ASIC issues a RESET signal to the TPS53667 device, as shown in Figure 17. The device senses this signal and after a delay of greater than 1 µs, it sets an internal RESET_FAULT signal and sets VOUT_COMMAND to VBOOT. The device pulls the output voltage to the VBOOT level with the slew rate set by SLEW-MODE pin, as shown in Figure 18.

When the RESET pin signal goes high, the internal RESET_FAULT signal goes low.

Figure 17. RESET Pin Connection

Figure 18. Reset Function

7.3.14 Input UVLO

The TPS53667 device continuously monitors the input voltage through the VIN pin. If the input voltage is lower than the UVLO low threshold, the device turns off. If V_IN rises higher than the UVLO high threshold, the controller turns on again (if both V5 and ENABLE are high). The hysteresis is approximately 1.05 V.

Table 2. Input Undervoltage Lockout (UVLO)

VIN UVLO SETTING	TURN-ON VOLTAGE (V)	TURN-OFF VOLTAGE (V)
MFR_SPEC_16[1:0] = 00	4.5	3.5
MFR_SPEC_16[1:0] = 01 (Default)	7.25	6.25
MFR_SPEC_16[1:0] = 10	7.9	6.9
MFR_SPEC_16[1:0] = 11	10.3	9.3

7.3.15 V5 Pin Undervoltage Lockout (UVLO)

The TPS53667 device also monitors V5 pin voltage. If the voltage is lower than V_V5UVLOL (4.05 V typical), the controller turns off. If V5 voltage comes back to be higher than V_V5UVLOH (4.25 V typical), the controller turns back on (if both VIN and ENABLE are high).

7.3.16 Output Undervoltage Protection (UVP)

The output undervoltage protection in the TPS53667 device is called tracking UVP. When the output voltage drops below (VDAC–V_DROOP–V_RDYL), the controller drives the PWM into a tri-state condition so that both high-side and low-side MOSFETs turn off. After a hiccup delay (22-ms typical), the device attempts to restart to VBOOT voltage. If the UVP condition continues, the UVP occurs again and the process repeats.

7.3.17 Overvoltage Protection (OVP)

The OVP condition is detected when the output voltage V_OUT > V_DAC+ tracking OVP offset (V_OVPT5 for VR12.5 or V_OVPT0 for VR12.0) , which is called tracking OVP. In this case the controller drives the VR_RDY pin to inactive (low state) and drives all PWM signals to logic low which turns on the low-side MOSFET to discharge the output. However the OVP threshold is blanked during a V_DAC change. In order to continually protect the load, there is second OVP level (fixed OVP). The second OVP level is fixed at V_OVPH5 (VR12.5) or V_OVPH0 (VR12.0) is active during VDAC change. If the fixed OVP condition is detected, the device drives the VR_RDY pin to inactive (logic low) and drives the PWM signals to logic low in order to turn on the low-side MOSFET. The controller remains in this state until the ENABLE or V5 is re-cycled.

For both tracking OVP and fixed OVP, the controller will try to restart after a hiccup delay (~22ms). If the OV condition still exists, the controller will pull PWM signal to logic low and enter into anther hiccup cycle. If after 3 hiccup cycles, the OV condition still exists, the controller will latch PWM signal to logic low until ENABLE or V5 is re-cycled.

When ENABLE is low, and output voltage is higher than V_OVPFP (2.75 V typical), the OVP condition is detected, which is called Pre-bias OVP. The device then drives the PWM signals to logic low. The device latches the pre-bias OVP. The latch can be cleared only by recycling V5.

7.3.18 Overcurrent Limit (OCL) and Overcurrent Protection (OCP)

The TPS53667 device includes a valley-current-based limit function by using a per-phase OCL comparator. A resistor connected between the OCL-R pin and the VREF pin generates the OCL comparison threshold.

Using the valley current limit, the OCL current level can be selected using Equation 5. To set the per-phase OCL threshold, subtract half of the ripple current from the maximum average current and select the OCL threshold specified in the table equal or slight lower than I_OCL.

Equation 5. TPS53667 q_iocl_lusbz3.gif

where

K is the maximum operating margin percentage
n is the number of active phases
I_RIPPLE is the ripple current

This instantaneous current sense voltage V_CSPx is compared to the OCL threshold. If the current sense voltage at OCL comparator goes above the OCL threshold, the device delays the next ON pulse until the current sense voltage drops below the OCL threshold. In this case, the output voltage continues to drop until the UVP threshold is reached.

Another overcurrent protection (OCP) is based on the current sensed through IMON pin of the device. When the digitized IMON is higher than OC_FAULT_LIMIT (1.25× IMAX by default), the controller turns off both high-side and low-side MOSFETS and enters into hiccup mode until the overcurrent condition is removed.

7.3.19 Current Sharing Warning and Phase Fault Detect

TPS53667 can detect faulty phases with the current sharing warning feature. If the current of a certain phase is lower than the average current by certain threshold (set by MFR_SPECiFIC_19, default is 8A), the controller can turn off the faulty phase while keeping the other phases in operation (This is also configurable by MFR_SPECIFIC_19[7]). The faulty phase can be read from STATUS_MFR_SPECIFIC[5:3].

The phase interleaving is not adjusted when the faulty phase is turned off. The controller phase interleaving operates as if the faulty phase still is still operating. This behavior has the affect of slightly increasing the output voltage ripple.

When there are only two phases in operation, this feature is disabled. For example, even if one of the phases has current lower than average, it does not turn off.

7.3.20 Turn off Individual Phase by PMBus

Individual phases can also be turned off by using the PMBus command MFR_SPECIFIC_24(0xE8). Please see MFR_SPECIFIC_24 (E8h)section for more details.

The MFR_SPECIFIC_24 setting can be effective before the controller is enabled. For example, when a certain phase is turned off by MFR_SPECIFIC_24 before Enable goes high, this phase does not turn on after Enable.

7.3.21 Phase Shedding

Phase Shedding is enabled with MFR_SPECIFIC_13[4]. Phase shedding allows the user to optimize efficiency over a wider range of loads. Using only one or two phases is often more efficient when the load is drawing a smaller amount of current, than using all six phases.

The points at which phases are shed can be set by MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh).

7.3.22 Over Temperature Protection (OTP)

When the sensed temperature through TSEN pin is higher than the over temperature fault threshold OTP_THLD(125°C by default), the controller turns off high-side and low-side MOSFETS. The power stages cool down and TSEN voltage drops. When the sensed temperature is 15°C (OTP_HYS) lower than the over temperature fault threshold, the controller restarts to the VBOOT voltage.

7.3.23 VR_HOT and VR_FAULT Indication

When the sensed temperature is higher than the maximim temperature specification T_MAX,(110°C by default), the device pulls the VR_HOT pin low. This adjustment provides a warning signal to the load.

NOTE

Only the PMBus interface can establish the maximum temperature (T_MAX) setting. NVM does not store this setting.

VR_FAULT is used as an indication of severe fault. VR_FAULT wil be pulled low when the below fault occurs:

Input Overcurrent Fault
Over Temperature Fault
Overvoltage Fault
Power Stage Fault (V_TSEN> 2.5V)

7.4 Device Functional Modes

Table 3. Maximum Operating Phase Numbers

CSP1	CSP2	CSP3	CSP4	CSP5	CSP6	MAXIMUM ACTIVE PHASES
IOUT1	V3R3	n/a	n/a	n/a	n/a	1
IOUT1	IOUT2	V3R3	n/a	n/a	n/a	2
IOUT1	IOUT2	IOUT3	V3R3	n/a	n/a	3
IOUT1	IOUT2	IOUT3	IOUT4	V3R3	n/a	4
IOUT1	IOUT2	IOUT3	IOUT4	IOUT5	V3R3	5
IOUT1	IOUT2	IOUT3	IOUT4	IOUT5	IOUT6	6

7.5 Programming

7.5.1 User Selections

When SKIP-NVM pin is connected to GND with ≤ 20-kΩ resistor, the resistors connected to O-USR, F-IMAX, SLEW-MODE, OCL-R, VBOOT and ADDR-TRISE determine the associated configurations. If SKIP-NVM pin is connected to GND with ≥ 100-kΩ resistor, these configurations are determined by NVM settings. Please note the address setting is determined only by the resistors on the ADDR-TRISE pin and cannot be set by NVM. When the V3R3 pin powers up, the following information is latched for normal operations, and can be changed via the PMBus interface. The Electrical Characteristics table defines the values of the selections.

In general, the NVM provides more selection than pinstrap configurations. For example, pinstrap for switching frequency offers 3-bit, 8 selections, which correlates to MFR_SPEC_12<6:4>. Alternatively, NVM provides 4-bit, 16 selections.

7.5.1.1 Switching Frequency

The resistor from F-IMAX pin to GND sets the switching frequency from 300 kHz to 1 MHz. See the Electrical Characteristics table for the resistor settings corresponding to each frequency selection. Please note that the operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage (at the VIN pin) and output voltage (set by VID). The OFF time varies based on various factors such as load and power-stage components.

7.5.1.2 IMAX Information

The max current information of the load(IMAX) can be set by the voltage on the F-IMAX pin. See the Electrical Characteristics table for the details. The default OCP fault trigger level is 125% of IMAX.

7.5.1.3 Boot Voltage

The boot voltage is the controller voltage at start-up to before any output voltage change by the VOUT_COMMAND. If there is no further output voltage adjustment, the output voltage remains at the boot voltage level.

The resistor from the VBOOT pin to GND and the voltage level on this pin set 7 high bits of the boot voltage. The lowest bit is set by the ADDR-TRISE pin. See the Electrical Characteristics table for the resistor settings corresponding to boot voltage selections.

7.5.1.4 Per-Phase Overcurrent Limit (OCL) Level

The resistor from the OCL-R pin to GND and the voltage level on this pin set the per-phase OCL level. See the Electrical Characteristics table for the details.

7.5.1.5 Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels

The resistor from the O-USR pin to GND and the voltage on O-USR pin set the OSR and USR levels. See the Electrical Characteristics table for details.

7.5.1.6 Slew Rate Selection

The V_OUT change slew rate is set by the resistor from the SLEW-MODE pin to GND. See the Electrical Characteristics table for details.

7.5.1.7 Mode Selections

The TPS53667 device supports different operating modes, including VR12.0/VR12.5, phase interleaving mode, dynamic phase shedding, and zero load-line. The voltage on SLEW-MODE pin sets the desired operating modes.

7.5.1.8 Soft Start Slew Rate and PMBus Addresses

The resistor from the ADDR-TRISE pin to GND and the voltage on ADDR-TRISE pin set the slew rate of soft start and the address of PMBus interface. See the Electrical Characteristics table for details.

7.5.1.9 Ramp Selection

The internal ramp can be set by the voltage on the OCL-R pin. See the Electrical Characteristics table for details.

7.5.1.10 Maximum Active Phase Numbers

The maximum active phase numbers can be selected by connecting CSP2, CSP3, CSP4, CSP5 or CSP6 to the V3R3. See Table 3 for details. The device latches this configuration when V3R3 powers up.

7.5.1.11 Pinstrap Mode Settings

Table 4 summarizes the functions controlled with pin-strap resistors. For details of each setting please refer to the Electrical Characteristics table. For more information on VID encoding see the VID section.

Table 4. Pinstrap Mode Summary

FUNCTION	PIN		DESCRIPTION
FUNCTION	NAME	NO.	DESCRIPTION
Slew Rate	SLEW-MODE	29	Voltage divider to VREF pin. A pin-strap resistor (R_SLEW-MODE) connected between this pin and GND sets one of eight possible slew rates.
Mode	SLEW-MODE	29	The voltage level (V_SLEW-MODE) sets 4-bit operation modes. -Bit 7 for DAC mode (1 for VR12.0; 0 for VR12.5). -Bit 6 for the 4-phase interleaving mode (1 for 1/3 and 2/4 two phase interleaving; 0 for 4 phase interleaving individually). -Bit 4 for enabling dynamic phase add or drop (1 for enable; 0 for disable). -Bit 3 sets zero load-line (1 for zero load-line; 0 for non-zero load-line) The device latches these settings when V3R3 powers up.
Overshoot reduction	O-USR	30	Voltage divider to VREF pin. A pin-strap resistor (R_O-USR) connected between this pin and GND selects 1 of 7 OSR thresholds or OFF.
Undershoot reduction	O-USR	30	The voltage level (V_O-USR) sets 1 of 7 USR levels or OFF. The device latches these settings when V3R3 powers up.
Voltage boot	VBOOT	31	Voltage divider to VREF pin. A pin-strap resistor (R_VBOOT) connected between this pin and GND sets 3 bits (B[3:1]). The voltage level (V_BOOT) sets 4 bits (B[7:4]). The total 7 bit sets 7 of 8 bits of VID of VBOOT(B[7:1]). The device latches these settings when V3R3 powers up.
Voltage boot	ADDR-TRISE	28	Voltage divider to VREF pin. A pin-strap resistor (R_ADDR-TRISE) connected between this pin and GND sets 3-bits. -Bit 2 and Bit 1 set the rise slew rate (TRISE). -Bit 0 Selects the LSB of BOOT voltage. The voltage (V_ADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up.
Rise slew rate	ADDR-TRISE	28	Voltage divider to VREF pin. A pin-strap resistor (R_ADDR-TRISE) connected between this pin and GND sets 3-bits. -Bit 2 and Bit 1 set the rise slew rate (TRISE). -Bit 0 Selects the LSB of BOOT voltage. -The voltage (V_ADDR-TRISE) sets 4 bits PMBus address. The device latches these settings when V3R3 powers up
Frequency	F-IMAX	32	Voltage divider to VREF pin. A pin-strap resistor (R_F-IMAX) connected between this pin and GND sets the operating frequency of the controller.
Current limit	F-IMAX	32	The voltage level (V_F-IMAX) sets the maximum operating current of the converter. The IMAX value is an 8-bit A/D where V_F-IMAX= V_VREF × IMAX / 255. Both are latched at V3R3 power-up.
Overcurrent limit	OCL-R	1	Voltage divider to VREF pin. A pin-strap resistor (R_OCL-R) connected between this pin and GND and the voltage level (V_OCL-R) selects one of 16 OCL levels (per phase current-limit).
Ramp	OCL-R	1	V_OCL-R sets one of four RAMP levels. The device latches these settings when the V3R3 pin powers up.

7.5.1.12 NVM Default Settings

Table 5 lists the default settings in NVM where the shaded rows denote register functions that are configured by associated pins in pinstrap mode.

Table 5. NVM Default Settings

REGISTER	FUNCTION	DEFAULT VALUES
REGISTER	FUNCTION	bit 7	bit 6	bit 5	bit 4	bit 3	bit 2	bit 1	bit 0
MFR_SPECIFIC_13 [2:0]	Slew Rate	—					0	0	1
MFR_SPECIFIC_13 [7:3]	Mode	1	0	0	0	1	—
MFR_SPECIFIC_09 [2:0]	OSR	—					1	1	1
MFR_SPECIFIC_09 [6:4]	USR	—	1	1	1	—
MFR_SPECIFIC_11 [7:0]	VBOOT	1	0	0	1	0	1	1	1
MFR_SPECIFIC_12 [1:0]	TRISE	—						0	0
MFR_SPECIFIC_12[7:4]	Frequency	0	0	1	0	—
MFR_SPECIFIC_10 [7:0]	IMAX	1	0	1	1	0	1	0	0
MFR_SPECIFIC_00 [3:0]	OCL	—				1	0	0	0
MFR_SPECIFIC_14[2:0]	RAMP	—					1	1	0
MFR_SPECIFIC_07 [0]	Soft-start slew rate	—							0
MFR_SPECIFIC_07 [1]	OSR_TRISTATE	—						1	—
MFR_SPECIFIC_07 [2]	SLEW_FAST	—					0	—
MFR_SPECIFIC_07 [3]	Power Stage Fault Disable	—				0	—
MFR_SPECIFIC_07 [4]	OV Hiccup Disable	—			0	—
MFR_SPECIFIC_16 [1:0]	VIN UVLO	—					0	1
MFR_SPECIFIC_15 [3]	DPS_TH_LOW	—				1	—
MFR_SPECIFIC_15 [2:0]	DPS_TH_HIGH	—					0	0	1
MFR_SPECIFIC_19 [3]	Current Sharing Warning Response	—				0	—
MFR_SPECIFIC_19 [2:0]	Current Sharing Warning Threshold	—					0	1	1
MFR_SPECIFIC_21 [4:3]	Tracking OV OFFSET	—			0	1	—
MFR_SPECIFIC_21 [2:0]	Fixed OV OFFSET	—					1	1	1
MFR_SPECIFIC_22 [2:0]	UV OFFSET	—					0	1	1
MFR_SPECIFIC_05 [7:0]	VOUT OFFSET	0	0	0	0	0	0	0	0
MFR_ID	—	0	1	0	1	0	1	0	0
MFR_MODEL		0	1	0	0	0	1	1	1
MFR_REVISION [3:0]		—				0	0	0	0
MFR_DATE		0	0	0	0	0	0	0	0

7.5.1.13 6-Phase Application

Figure 19 shows the diagram for a 6-Phase application with smart power stage (CSD95490Q5MC) and pinstrap configurations.

Figure 19. 6-Phase Application with Smart Power Stage (CSD95490Q5MC) and Pinstrap Configuration

7.5.1.14 6-Phase NVM Application

Figure 20 shows the diagram for a 6-Phase application with smart power stage (CSD95490Q5MC) and NVM configurations.

Figure 20. 6-Phase Application with Smart Power Stage (CSD95490Q5MC) and NVM Configuration

7.5.2 Supported Protections and Fault Reports

The TPS53667 device supports different types of fault protections, and the warning or fault reports can be found in the corresponding PMBus registers. The TPS53667 also supports VR_FAULT to indicate catastrophic faults to the system. If the fault causes the controller to latch-off, then V5 or EN re-cycling is required to clear the latched faults. Only V5 recycling can clear PRE_OVF .

Table 6. Supported Protections and Fault Reports

FAULT NAME	DESCRIPTIONS	LATCH-OFF	ALERT	REPORT
VOLTAGE
PRE_OVF	V_OUT > V_OVPFP	Y	VR_FAULT PMB_ALERT	PMBus
OVF	V_OUT > VID + V_OVPT5/0 or V_OUT> V_OVPF5	Y	VR_FAULT PMB_ALERT	PMBus
UVF	V_OUT < VID – V_RDYL – V_DROOP	N	PMB_ALERT	PMBus
VIN_OVF	V_VIN > VIN_OV_FAULT_LIMIT when the controller is enabled	N	PMB_ALERT	PMBus
VIN_UVF	V_VIN < V_INUVLO when the controller is enabled	N	PMB_ALERT	PMBus
CURRENT
OCF	I_OUT ≥ IOUT_OC_FAULT_LIMIT	N	PMB_ALERT	PMBus
OCW	I_O ≥ IOUT_OC_WARN_LIMIT	N	PMB_ALERT	PMBus
IOCF	I_IN≥ IIN_OC_FAULT_LIMIT	Y	VR_FAULT PMB_ALERT	PMBus
IOCW	I_IN ≥ IIN_OC_WARN_LIMIT	N	PMB_ALERT	PMBus
TEMPERATURE
OTF	T_sen ≥ OT_FAULT_LIMIT	N	VR_FAULT PMB_ALERT	PMBus
OTW	T_sen ≥ OT_WARNING_LIMIT	N	PMB_ALERT	PMBus
TMAX_F	T_sen≥ T_MAX	N	VR_HOT
TS_VREFF	TSEN pin short to VREF	Y	PMB_ALERT	PMBus
TS_GND	TSEN pin short to GND	Y	PMB_ALERT	PMBus
TS_PS	V_TSEN > 2.5 V	Y	VR_FAULT PMB_ALERT	PMBus

7.5.3 Supported PMBus Address and Commands Summary

7.5.3.1 Address Selection

The TPS53667 device has a dedicated pin (ADDR-TRISE) for determining the address for the PMBus communication. The device supports a total of 16 possible addresses. See the Electrical Characteristics table for details.

7.5.3.2 Commands Summary

The TPS53667 device supports only PMBus command sets listed in Table 7. In pinstrap mode, the default state of all the configuration registers (shaded rows in Table 5) should be detected from pinstrap settings, but users can overwrite the settings via PMBus after the power-up sequence is complete. In NVM mode, the default values can be found in the register descriptions.

Table 7. Supported PMBus Commands

CODE	COMMAND NAME	TYPE	DESCRIPTION: PMBus Command	FACTORY DEFAULT VALUE
01h	OPERATION	R/W Byte	Turn the unit on and off in conjunction with the input from the ENABLE pin. Set the output voltage to the upper or lower MARGIN voltages.	00h
02h	ON_OFF_CONFIG	R/W Byte	Configures the combination of CONTROL pin input and serial bus commands needed to turn the unit on and off. This includes how the unit responds when power is applied.	17h
03h	CLEAR_FAULTS	Send Byte	Clears any faults bits that have been set if the fault is no longer present. At the same time, simultaneously clears all bits in all status registers and negates the PMB_ALERT signal output if it is asserted.	NONE
10h	WRITE_PROTECT	R/W Byte	Used to control writing to the PMBus device. Can be used to prevent unwanted writes to the device.	00h
11h	STORE_DEFAULT_ALL	Send Byte	Store the settings to the NVM.	NONE
12h	RESTORE_DEFAULT_ALL	Send Byte	Restore the settings from the NVM.	NONE
19h	CAPABILITY	Read Byte	Provides a way for the host to determine the capabilities of the PMBus device.	B0h
20h	VOUT_MODE	Read Byte	Read-Only VOUT Mode Indicator.	21h
21h	VOUT_COMMAND	R/W Word	Causes the device to set its output voltage to the commanded value.	VBOOT
24h	VOUT_MAX	R/W Word	Sets the upper limit on the output voltage the unit can command regardless of any other commands or combinations. Provides a safeguard against a user accidentally setting the output voltage to a possibly destructive level.	00FFh
25h	VOUT_MARGIN_HIGH	R/W Word	Loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to "Margin High."	0000h
26h	VOUT_MARGIN_LOW	R/W Word	Loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to "Margin Low."	0000h
39h	IOUT_CAL_OFFSET	R/W Word	compensate for offset errors in READ_VOUT command.	0000h
41h	VOUT_OV_FAULT_RESPONSE	Read Byte	Instructs the device on what action to take in response to an output overvoltage fault.	9Ah
45h	VOUT_UV_FAULT_RESPONSE	Read Byte	Instructs the device on what action to take in response to an output undervoltage fault.	BAh
46h	IOUT_OC_FAULT_LIMIT	R/W Word	Sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent fault condition.	125% IMAX
47h	IOUT_OC_FAULT_RESPONSE	Read Byte	Instructs the device on what action to take in response to an output overcurrent fault.	FAh
4Ah	IOUT_OC_WARN_LIMIT	R/W Word	Sets the value of the output current that causes an output overcurrent warning condition.	IMAX
4Fh	OT_FAULT_LIMIT	R/W Word	Sets the temperature, in degree Celsius, that causes an over-temperature fault condition.	007Dh
50h	OT_FAULT_RESPONSE	Read Byte	Instructs the device on what action to take in response to an output over-temperature fault.	F8h
51h	OT_WARN_LIMIT	R/W Word	Sets the temperature, in degrees Celsius, that causes an over-temperature warning condition.	005Fh
55h	VIN_OV_FAULT_LIMIT	R/W Word	Sets the input voltage, in volts, that causes an overvoltage fault condition.	0011h
5Bh	IIN_OC_FAULT_LIMIT	R/W Word	Sets the input current, in amperes, that causes an overcurrent fault condition.	00FFh
5Ch	IIN_OC_FAULT_RESPONSE	Read Byte	Instructs the device on what action to take in response to an input overcurrent fault.	C0h
5Dh	IIN_OC_WARN_LIMIT	R/W Word	Sets the input current, in amperes, that causes an overcurrent warning condition.	0019h
78h	STATUS_BYTE	Read Byte	Single byte status indicator	Dependent on the Startup Condition
79h	STATUS_WORD	Read Word	Full 2-byte status indicator	Dependent on the Startup Condition
7Ah	STATUS_VOUT	Read Byte	Output voltage fault status detail	Dependent on the Startup Condition
7Bh	STATUS_IOUT	Read Byte	Output current fault status detail	Dependent on the Startup Condition
7Ch	STATUS_INPUT	Read Byte	Input voltage and current fault status detail	Dependent on the Startup Condition
7Dh	STATUS_TEMPERATURE	Read Byte	Temperature fault status detail	Dependent on the Startup Condition
7Eh	STATUS_CML	Read Byte	Communication, memory, and logic fault status detail	Dependent on the Startup Condition
80h	STATUS_MFR_SPECIFIC	Read Byte	Manufacturer specific fault status detail	Dependent on the Startup Condition
88h	READ_VIN	Read Word	Read input voltage, in volts.
89h	READ_IIN	Read Word	Read input current, in amperes.
8Bh	READ_VOUT	Read Word	Read output voltage, in volts.
8Ch	READ_IOUT	Read Word	Read output current, in amperes.
8Dh	READ_TEMPERATURE_1	Read Word	Read temperature, in degrees Celsius.
96h	READ_POUT	Read Word	Read output power, in watts.
97h	READ_PIN	Read Word	Read input power, in watts.
98h	PMBUS_REVISION	Read Byte	PMBus Revision Information	11h
99h	MFR_ID	Read Block	Loads the unit with the text character that contains the manufacturer's ID.	54h
9Ah	MFR_MODEL	Read Block	Loads the unit with the text character that contains the model number of the manufacturer.
9Bh	MFR_REVISION	Read Block	Loads the unit with the text character that contains the revision number of the manufacturer.
9Dh	MFR_DATE	Read Block	Loads the unit with the text character that contains the device's date of manufacture.
A4h	MFR_VOUT_MIN	R/W Word	Sets a low limit on the output voltage that the device can command regardless of any other commands or combinations. (VID data format)	0000h
D0h	MFR_SPECIFIC_00	R/W Byte	Selects the threshold for the per-phase current limit. (Fixed at PMBus control)	Pin strap: OCL-R pin NVM: 08h
D1h	MFR_SPECIFIC_01	R/W Byte	Selects the averaging time for telemetry reporting.	50h
D4h	MFR_SPECIFIC_04	Read Word	Returns the actual, measured output voltage in volts.
D5h	MFR_SPECIFIC_05	R/W Byte	Used to trim the output voltage.	NVM: 00h
D7h	MFR_SPECIFIC_07	R/W Byte	Additional functional bits setting.	NVM: 02h
D8h	MFR_SPECIFIC_08	R/W Byte	Sets the droop as a percentage of the loadline.	04h
D9h	MFR_SPECIFIC_09	R/W Byte	Sets the threshold for OSR and USR control.	Pin strap: O-USR pin NVM: 77h
DAh	MFR_SPECIFIC_10	R/W Byte	Sets the maximum operating current, IMAX.	Pin strap: F-IMAX pin NVM: B4h
DBh	MFR_SPECIFIC_11	R/W Byte	Sets the boot voltage, VBOOT.	Pin strap: VBOOT pin NVM: 97h
DCh	MFR_SPECIFIC_12	R/W Byte	Sets the switching frequency and the rise time (t_RISE) settings.	Pin strap: F-IMAX and ADDR-TRISE pins NVM: 20h
DDh	MFR_SPECIFIC_13	R/W Byte	Sets the slew rate and other operation modes.	Pin strap: SLEW-MODE pin NVM: 89h
DEh	MFR_SPECIFIC_14	R/W Byte	Sets the ramp amplitude in mV.	Pin strap: OCL-R pin NVM: 06h
DFh	MFR_SPECIFIC_15	R/W Byte	Sets the threshold for dynamic phase shedding as a percentage of the OCL.	NVM: 09h
E0h	MFR_SPECIFIC_16	R/W Byte	Sets the threshold for the input voltage UVLO.	NVM: 01h
E3h	MFR_SPECIFIC_19	R/O Word	Sets the value of phase current imbalance warning limit. Limit is set within the range of 2A-16A. The two data bytes are formatted in Linear Data format. Upon detection, the device asserts SMBALERT#.	NVM: 0003h
E4h	MFR_SPECIFIC_20	R/W Byte	Sets the maximum number of operational phase numbers on the fly.	Hardware Specific
E5h	MFR_SPECIFIC_21	R/W Byte	Sets the over-voltage offsets.	NVM: 0Fh
E6h	MFR_SPECIFIC_22	R/W Byte	Sets the under-voltage offsets.	NVM: 03h
E7h	MFR_SPECIFIC_23	R/O Word	Sets VBOOT value with VID data format.
E8h	MFR_SPECIFIC_24	R/W Byte	Enable/Disable the Phases
FCh	MFR_SPECIFIC_44	Read Word	Returns DEVICE_CODE information	01F8h

7.6 Register Maps

7.6.1 PMBus Description

7.6.1.1 PMBus General

Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.1 available at http://PMBus.org. The TPS53667 device supports both the 100-kHz and 400-kHz bus timing requirements. The TPS53667 device does not stretch pulses on the PMBus when communicating with the master device.

Communication over the TPS53667 device PMBus interface can support the packet error checking (PEC) scheme if desired. If the master supplies CLK pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.

The TPS53667 device supports a subset of the commands in the PMBus 1.1 specification. Most of the controller parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the command and altering the exponent is not supported. Direct format data input or output is not supported by the TPS53667 device. See the Supported PMBus Commands section for specific details.

The TPS53667 device also supports the SMBALERT response protocol. The SMBALERT response protocol is a mechanism by which a slave (the TPS53667 device) can alert the bus master that it wants to talk. The master processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the alert response address. Only the slave that caused the alert acknowledges this request. The host performs a modified receive byte operation to get the slave’s address. At this point, the master can use the PMBus status commands to query the slave that caused the alert. For more information on the SMBus alert response protocol, see the System Management Bus (SMBus) specification.

The TPS53667 device contains non-volatile memory that is used to store configuration settings and scale factors. The settings programmed into the device are not automatically saved into this non-volatile memory though. The STORE_DEFAULT_ALL command must be used to commit the current settings to non-volatile memory as device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed descriptions.

7.6.1.2 PMBus Connections

The TPS53667 device can operate in either standard mode (100kbit/s) or fast mode (400kbit/s). Connection for the PMBus interface should follow the High Power DC specifications given in Section 3.1.3 of the System Management Bus (SMBus) Specification V2.0 for the 400-kHz bus speed or the Low Power DC specifications in Section 3.1.2. The complete SMBus specification is available from the SMBus website, smbus.org.

7.6.1.3 Supported Data Formats

The TPS53667 device supports both linear and VID data formats. The linear data format is used for all telemetry reporting data, and VID formatting for certain other commands. (see the Supported PMBus Commands section for more details on which command supports each data type). Examples of commands that support VID formatting include VOUT_MODE (Read-only Byte) and VOUT_COMMAND (Read/Write Word). An example of each can be seen below in Figure 21 and Figure 22.

TPS53667 pro_vout_mode_data_byte_slusaz3.gif

Figure 21. VOUT_MODE Data Byte for VID Mode

TPS53667 pro_vout_command_data_byte_slusaz3.gif

Figure 22. VOUT_COMMAND Data Bytes for VID Mode

The Linear Data Format is a two byte value with:

An 11-bit, two's complement mantissa, and
A 5-bit, two's complement exponent (scaling factor).

The format of the two bytes is shown in Figure 23.

TPS53667 pro_linear_data_byte_slusaz3.gif

Figure 23. Linear Data Format Data Bytes

The relation between Y, N, and the real world value is as shown in Equation 6.

Equation 6. X = Y × 2^N

where

X is the real world value
Y is an 11-bit, two's complement integer
N is a 5-bit, two's complement integer

Note that devices that use the Linear format must accept and be able to process any value of N.

7.6.1.4 PMBus Command Format

The TPS53667 device is a PMBus-compliant device. Figure 24 through Figure 35 show the major communication protocols used. For full details on the PMBus communication protocols, please visit http://pmbus.org.

Figure 24. Write Byte Protocol

Figure 25. Write Byte Protocol with PEC

Figure 26. Write Word Protocol

Figure 27. Write Word Protocol with PEC

Figure 28. Read Byte Protocol

Figure 29. Read Byte Protocol with PEC

Figure 30. Read Word Protocol

Figure 31. Read Word Protocol with PEC

Figure 32. Block Write Protocol

Figure 33. Block Write Protocol with PEC

Figure 34. Block Read Protocol

Figure 35. Block Read Protocol with PEC

7.6.2 PMBus Functionality

7.6.2.1 PMBus Address

The TPS53667 device has a dedicated pin (ADDR-TRISE) for determining the address for the PMBus communication. The device supports a total of 16 possible addresses as listed in the Electrical Characteristics table.

7.6.2.2 Pin Strap Settings

The TPS53667 device supports only PMBus command sets listed in the Electrical Characteristics table. In pinstrap mode, the default state of all the configuration registers should be detected from pin strap settings, but users can overwrite the settings via PMBus after the power-up sequence is complete. The pin strap settings can be found in the Electrical Characteristics table.

7.6.2.3 Supported PMBus Commands

The TPS53667 device supports the following commands from the PMBus 1.1 specification.

7.6.2.3.1 OPERATION (01h)

Format	N/A
Description	The OPERATION command is used to turn the device output on or off in conjunction with the input from the ENABLE pin. It is also used to set the output voltage to the upper or lower MARGIN levels.
Default	00h

Figure 36. OPERATION Register

7	6	5	4	3	2	1	0
ON_OFF	SOFT_OFF	OPMARGIN				IIN_OC_VRHOT
R/W	R-0	R/W				R/W

Table 8. OPERATION Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	ON_OFF	R/W	0	—	The On/Off bit is used to enable the IC via PMBus. The necessary condition for this bit to be effective is that the CMD bit in the ON_OFF CONFIG register is set high. However, the CMD bit being high is not a sufficient condition to enable the IC via the On bit, as specified below: 0: (Default) The device output is not enabled via PMBus. 1: The device output is enabled if: MMMa. The supply voltage VIN is greater than the VIN_UVLO threshold, the cmd bit is high, and MMMb. The bit CP in the ON_OFF CONFIG register is low, or MMMc. The bit CP is high and the ENABLE pin is asserted.
6	SOFT_OFF	R	0	—	This bit is not supported and always set to 0 on this device. 0: No Soft off 1: Not Supported.
5-2	OPMARGIN	R/W	0	—	If Margin Low is enabled, load the value from the VOUT_MARGIN_LOW register. If Margin High is enabled, load the value from the VOUT_MARGIN_HIGH register. 00xx: Turn off VOUT margin function 0101: Turn on VOUT margin low and ignore fault 0110: Turn on VOUT margin low and act on fault 1001: Turn on VOUT margin high and ignore fault 1010: Turn on VOUT margin high and act on fault
1-0	IIN_OC_VRHOT	R/W	00	—	This bit sets the option of asserting VRHOT when IIN_OC_WARN_LIMIT is detected. 01: VRHOT assertion ON with IIN_OC_WARN_LIMIT detection others: VRHOT assertion OFF with IIN_OC_WARN_LIMIT detection

7.6.2.3.2 ON_OFF_CONFIG (02h)

Format	N/A
Description	The ON_OFF_CONFIG command configures the combination of CONTROL pin input and serial bus commands needed to turn the unit on and off. This includes how the unit responds when power is applied.
Default	17h

Figure 37. ON_OFF_CONFIG Register

7	6	5	4	3	2	1	0
Reserved			PU	CMD	CP	PL	SP
R-000			R-1	R/W	R/W	R-1	R-1

Table 9. ON_OFF_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7-5	Reserved	R	000	—	Always set to 0.
4	PU	R	1	—	This bit is not supported and always set to 1 on this device. 0: Not supported. 1: Device will act on ENABLE pin assertion and/or ON_OFF bit (OPERATION<7>).
3	CMD	R/W	0	—	The CMD bit controls how the device responds to the OPERATION<7> bit. 0: (Default) Device ignores the ON_OFF OPERATION<7> bit. 1: Device responds to the ON_OFF OPERATION<7> bit.
2	CP	R/W	1	—	The CP bit controls how the device responds to the ENABLE pin 0: Device ignores the ENABLE pin, and ON/OFF is controlled only by the OPERATION command 1: Device responds to the ENABLE pin.
1	PL	R	1	—	This bit is not supported and always set to 1 on this device. 0: Not supported. 1: ENABLE pin has active high polarity.
0	SP	R	1	—	This bit is not supported and always set to 1 on this device. 0: Not supported. 1: Turn off output as fast as possible.

7.6.2.3.3 CLEAR_FAULTS (03h)

Format	N/A
Description	Clears any faults bits that have been set. At the same time, simultaneously clears all bits in all status registers and negates the PMB_ALERT signal output if it is asserted. The CLEAR_FAULTS command does not cause a unit that has latched off for a condition to restart. If the fault remains present when the bit is cleared, the fault bit is reset and the host notified by the usual means.
Default	NONE

Figure 38. CLEAR_FAULTS Register

7	6	5	4	3	2	1	0
N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
—	—	—	—	—	—	—	—

Table 10. CLEAR_FAULTS Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7-0	N/A	—	—	—	No data bytes are sent, only the command code is sent.

7.6.2.3.4 WRITE_PROTECT (10h)

Format	N/A
Description	The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command has one data byte as described below. NOTE: Invalid data written to WRITE_PROTECT[7:5] causes the ’CML’ bit in the STATUS_BYTE and the ‘US_DATA’ bit in the STATUS_CML registers to be set. Invalid data also results in no write protection.
Default	00h

Figure 39. WRITE_PROTECT Register

7	6	5	4	3	2	1	0
bit7	bit6	bit5	Reserved
R/W	R/W	R/W	R-0 0000

Table 11. WRITE_PROTECT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	bit7	R/W	0	—	0: (Default) See Table 12. 1: Disable all writes except for the WRITE_PROTECT command (bit5 and bit6 must be 0 to be valid).
6	bit6	R/W	0	—	0: (Default) See Table 12. 1: Disable all writes except for the WRITE_PROTECT and OPERATION commands (bit5 and bit7 must be 0 to be valid).
5	bit5	R/W	0	—	0: (Default) See Table 12. 1: Disable all writes except for the WRITE_PROTECT, OPERATION, and ON_OFF_CONFIG commands (bit6 and bit7 must be 0 to be valid).
4:0	Reserved	R	0 0000	—	Always set to 0.

Table 12. WRITE_PROTECT Data Byte Values

Data Byte Value	Action
1000 0000	Disables all writes except to the WRITE_PROTECT command.
0100 0000	Disables all writes except to the WRITE_PROTECT and OPERATION commands.
0010 0000	Disables all writes to the WRITE_PROTECT, OPERATION, ON_OFF_CONFIG and VOUT_COMMAND commands.
0000 0000	Enable writes to all commands
Others	Invalid data.

7.6.2.3.5 STORE_DEFAULT_ALL (11h)

Format

N/A

Description

The STORE_DEFAULT_ALL command instructs the PMBus device to copy the entire contents of the Operating Memory to the matching locations in the non-volatile Default Store memory. Any items in the Operating Memory that do not have matching locations in the Default Store are ignored.

Following a STORE_DEFAULT_ALL command, the following registers return to the default values regardless of the values in the Operating Memory:

OC_FAULT_LIMIT returns to 125%×IMAX,
OC_WARN_LIMIT returns to IMAX,
VOUT_COMMAND returns to VBOOT,
VOUT_MAX returns to 00FFh (1.52V in VR12.0 mode and 3.04 V in VR12.5 mode)

Default

NONE

Figure 40. STORE_DEFAULT_ALL Register

7	6	5	4	3	2	1	0
N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
—	—	—	—	—	—	—	—

Table 13. STORE_DEFAULT_ALL Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	N/A	—	—	—	No data bytes are sent, only the command code is sent.

7.6.2.3.6 RESTORE_DEFAULT_ALL (12h)

Format	N/A
Description	The RESTORE_DEFAULT_ALL command instructs the PMBus device to copy the entire contents of the non-volatile Default Store memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the Default Store. Any items in Default Store that do not have matching locations in the Operating Memory are ignored.
Default	NONE

Figure 41. RESTORE_DEFAULT_ALL Register

7	6	5	4	3	2	1	0
N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
—	—	—	—	—	—	—	—

Table 14. RESTORE_DEFAULT_ALL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	N/A	—	—	No data bytes are sent, only the command code is sent.

7.6.2.3.7 CAPABILITY (19h)

Format	N/A
Description	This command provides a way for a host system to determine some key capabilities of this PMBus device.
Default	B0h

Figure 42. CAPABILITY Register

7	6	5	4	3	2	1	0
PEC	SPD		PMBALERT	Reserved
R-1	R-01		R-1	R-0000

Table 15. CAPABILITY Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	PEC	R	1	—	Packet Error Checking is supported. 1: Default
6:5	SPD	R	01	—	Maximum supported bus speed is 400 kHz. 01: Default
4	PMBALERT	R	1	—	This device does have a PMBALERT pin and does support the SMBus Alert Response Protocol. 1: Default
3:0	Reserved	R	0000	—	Always set to 0.

7.6.2.3.8 VOUT_MODE (20h)

Format	VID
Description	The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit Mode and 5-bit parameter, as shown below. This command is read-only. If the host sends a VOUT_MODE command for writing, the device will reject the command and declare a communication fault for invalid data and respond as described in PMBus specification II section 10.2.2.
Default	21h

Figure 43. VOUT_MODE Register

7	6	5	4	3	2	1	0
DATA_MODE			DATA_PARAMETER
R-001			R

Table 16. VOUT_MODE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:5	DATA_MODE	R	001	—	001: VID mode.
4:0	DATA_PARAMETER	R	0 0001	—	00010: For VR12.5 Mode 00001: For VR12.0 Mode

7.6.2.3.9 VOUT_COMMAND (21h)

Format	VID
Description	VOUT_COMMAND causes the device to set its output voltage to the commanded value with two data bytes. These data bytes consist of a right-justified VID code with VID0 in bit 0 of the lower data byte, VID1 in bit 1 of the lower byte and so forth. The VID table mapping is determined by the selected VID protocols (VR12.0 or VR12.5) from SLEW_MODE pin or MFR_SPECIFIC_13.
Default	VBOOT

Figure 44. VOUT_COMMAND Register

15	14	13	12	11	10	9	8
Reserved
R-0000 0000

7	6	5	4	3	2	1	0
VOUT
R/W

Table 17. VOUT_COMMAND Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	—	Always set to 0.
7:0	VOUT	R/W		—	Used to set the commanded VOUT. Cannot be set to a level above the value set by VOUT_MAX.

7.6.2.3.10 VOUT_MAX (24h)

Format	VID
Description	The VOUT_MAX command sets an upper limit on the output voltage that the unit can command regardless of any other commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly destructive level. The device detects that an attempt has been made to program the output to a voltage greater than the value set by the VOUT_MAX command. This will then be treated as a warning condition and not a fault condition. If an attempt is made to program the output voltage higher than the limit set by this command, the device responds as follows: The commanded output voltage is set to VOUT_MAX, The OTHER bit is set in the STATUS_BYTE, The VOUT bit is set in the STATUS_WORD, The VOUT_MAX warning bit is set in the STATUS_VOUT register, and The device notifies the host (asserts PMBUS_ALERT). The data bytes are two bytes, which are in right-justified VID format. The VID table mapping determined by the selected VID protocols (VR12.0 or VR12.5) from the SLEW_MODE pin or MFR_SPECIFIC_13.
Default	00FFh .

Figure 45. VOUT_MAX Register

15	14	13	12	11	10	9	8
Reserved
R-0000 0000

7	6	5	4	3	2	1	0
VOUT_MAX
R/W

Table 18. VOUT_MAX Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	—	Always set to 0.
7:0	VOUT_MAX	R/W	1111 1111	—	Used to set the maximum VOUT of the device.

7.6.2.3.11 VOUT_MARGIN_HIGH (25h)

Format	VID
Description	The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to Margin High. The data bytes are two bytes, which are in right-justified VID format. The VID table mapping determined by the selected VID protocols from the SLEW_MODE pin or MFR_SPECIFIC_13.
Default	0000h

Figure 46. VOUT_MARGIN_HIGH Register

15	14	13	12	11	10	9	8
Reserved
R-0000 0000

7	6	5	4	3	2	1	0
VOUT_MARGIN_HIGH
R/W

Table 19. VOUT_MARGIN_HIGH Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	—	Always set to 0.
7:0	VOUT_MARGIN_HIGH	R/W	0000 0000	—	Used to set the value for the VOUT Margin High.

7.6.2.3.12 VOUT_MARGIN_LOW (26h)

Format	VID
Description	The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when the OPERATION command is set to Margin Low. The data bytes are two bytes, which are in right-justified VID format. The VID table mapping determined by the selected VID protocols from the SLEW_MODE pin or MFR_SPECIFIC_13.
Default	0000h

Figure 47. VOUT_MARGIN_LOW Register

15	14	13	12	11	10	9	8
Reserved
R-0000 0000

7	6	5	4	3	2	1	0
VOUT_MARGIN_LOW
R/W

Table 20. VOUT_MARGIN_LOW Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	—	Always set to 0.
7:0	VOUT_MARGIN_LOW	R/W	0000 0000	—	Used to set the value for the VOUT Margin Low.

7.6.2.3.13 IOUT_CAL_OFFSET (39h)

Format	Linear
Description	The IOUT_CAL_OFFSET command sets the value of compensation for offset errors in the READ_IOUT command, in amperes.
Default	0000h

Figure 48. IOUT_CAL_OFFSET Register

15	14	13	12	11	10	9	8
IOCAL_OFS_EXPONENT					IOCAL_OFS_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
IOCAL_OFS_MANTISSA
R/W

Table 21. IOUT_CAL_OFFSET Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	IOCAL_OFS_EXPONENT	R/W		—	5-bit, two's complement exponent (scaling factor).
10:0	IOCAL_OFS_MANTISSA	R/W		—	11-bit, two's complement mantissa.

7.6.2.3.14 VOUT_OV_FAULT_RESPONSE (41h)

Format	N/A
Description	The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. Upon triggering the overvoltage fault, the controller is latched off, and the following actions are taken: Set the VOUT_OV_FAULT bit in the STATUS_BYTE, Set the VOUT bit in the STATUS_WORD, Set the VOUT_OV_FAULT bit in the STATUS_VOUT register, and The device notifies the host (asserts PMB_ALERT).
Default	9Ah

Figure 49. VOUT_OV_FAULT_RESPONSE Register

7	6	5	4	3	2	1	0
VOUT_OV_FAULT_RESPONSE
R-1000 0000

Table 22. VOUT_OV_FAULT_RESPONSE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	VOUT_OV_FAULT_RESPONSE	R	1000 0000	—	Upon triggering the overvoltage fault, the controller will shut the device down immediately and will not attempt to restart. The output remains disabled until the fault is cleared.

7.6.2.3.15 VOUT_UV_FAULT_RESPONSE (45h)

Format	N/A
Description	The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output undervoltage fault. Upon triggering the undervotlage fault, the following actions are taken: Set the OTHER bit in the STATUS_BYTE, Set the VOUT bit in the STATUS_WORD, Set the VOUT_UV_FAULT bit in the STATUS_VOUT register, and The device notifies the host (asserts PMB_ALERT).
Default	BAh

Figure 50. VOUT_UV_FAULT_RESPONSE Register

7	6	5	4	3	2	1	0
VOUT_UV_FAULT_RESPONSE
R-1011 1010

Table 23. VOUT_UV_FAULT_RESPONSE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	VOUT_UV_FAULT_RESPONSE	R	1011 1010	—	Upon triggering the undervoltage fault, the controller will shut the device down immediately and will attempt to restart after a 22 ms delay.

7.6.2.3.16 IOUT_OC_FAULT_LIMIT (46h)

Format	Linear
Description	The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes an overcurrent fault condition. Upon triggering the overcurrent fault, the following actions are taken: Set the IOUT_OC_FAULT bit in the STATUS_BYTE, Set the IOUT bit in the STATUS_WORD, Set the IOUT_OC_FAULT bit in the STATUS_IOUT register, and The device notifies the host (asserts PMB_ALERT).
Default	125% IMAX

Figure 51. IOUT_OC_FAULT_LIMIT Register

15	14	13	12	11	10	9	8
OCF_LIMIT_EXPONENT					OCF_LIMIT_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
OCF_LIMIT_MANTISSA
R/W

Table 24. IOUT_OC_FAULT_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	OCF_LIMIT_EXPONENT	R/W		—	5-bit, two's complement exponent (scaling factor).
10:0	OCF_LIMIT_MANTISSA	R/W		—	11-bit, two's complement mantissa.

7.6.2.3.17 IOUT_OC_FAULT_RESPONSE (47h)

Format	N/A
Description	The IOUT_OC_FAULT_RESPONSE instructs the device on what action to take in response to an output overcurrent fault. Upon triggering the overcurrent fault, the controller is latched off, and the following actions are taken: Set the IOUT_OC_FAULT bit in the STATUS_BYTE, Set the IOUT bit in the STATUS_WORD, Set the IOUT_OC_FAULT bit in the STATUS_IOUT register, and The device notifies the host (asserts PMB_ALERT).
Default	FAh

Figure 52. IOUT_OC_FAULT_RESPONSE Register

7	6	5	4	3	2	1	0
IOUT_OC_FAULT_RESPONSE
R-1111 1010

Table 25. IOUT_OC_FAULT_RESPONSE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	IOUT_OC_FAULT_RESPONSE	R	1111 1010	—	Upon triggering the overcurrent fault, the controller immediately shuts down the device and attempts to restart after a 22 ms delay.

7.6.2.3.18 IOUT_OC_WARN_LIMIT (4Ah)

Format	Linear
Description	The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes an output overcurrent warning condition. Upon triggering the overcurrent warning, the following actions are taken: Set the OTHER bit in the STATUS_BYTE, Set the IOUT bit in the STATUS_WORD, Set the IOUT OC Warning bit in the STATUS_IOUT register, and The device notifies the host (asserts PMB_ALERT).
Default	IMAX

Figure 53. IOUT_OC_WARN_LIMIT Register

15	14	13	12	11	10	9	8
OCW_LIMIT_EXPONENT					OCW_LIMIT_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
OCW_LIMIT_MANTISSA
R/W

Table 26. IOUT_OC_WARN_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	OCW_LIMIT_EXPONENT	R/W		—	5-bit, two's complement exponent (scaling factor).
10:0	OCW_LIMIT_MANTISSA	R/W		—	11-bit, two's complement mantissa.

7.6.2.3.19 OT_FAULT_LIMIT (4Fh)

Format	Linear
Description	The OT_FAULT_LIMIT command sets the value of the temperature limit, in degrees Celsius, that causes an over-temperature fault condition. The default value is 125C°. Upon triggering the over-temperature fault, the following actions are taken: Set the TEMPERATURE bit in the STATUS_BYTE, Set the OT_FAULT bit in the STATUS_TEMPERATURE register, and The device notifies the host (asserts PMB_ALERT and VR_FAULT).
Default	007Dh

Figure 54. OT_FAULT_LIMIT Register

15	14	13	12	11	10	9	8
OT_LIMIT_EXPONENT					OT_LIMIT_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
OT_LIMIT_MANTISSA
R/W

Table 27. OT_FAULT_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	OT_LIMIT_EXPONENT	R/W	0000 0	—	5-bit, two's complement exponent (scaling factor).
10:0	OT_LIMIT_MANTISSA	R/W	000 0111 1101	—	11-bit, two's complement mantissa.

7.6.2.3.20 OT_FAULT_RESPONSE (50h)

Format	N/A
Description	The OT_FAULT_RESPONSE instructs the device on what action to take in response to an over-temperature fault. Upon triggering the over-temperature fault, the controller shuts off and attempts to restart when the temperature reduces by 15C°, and the following actions are taken: Set the TEMPERATURE bit in the STATUS_BYTE, Set the OT_FAULT bit in the STATUS_TEMPERATURE register, and The device notifies the host (asserts PMB_ALERT and VR_FAULT).
Default	F8h

Figure 55. OT_FAULT_RESPONSE Register

7	6	5	4	3	2	1	0
OT_FAULT_RESPONSE
R-1111 1000

Table 28. OT_FAULT_RESPONSE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	OT_FAULT_RESPONSE	R	1111 1000	—	Upon triggering the over-temperature fault, the device will shut down immediately (disables the output), and will restart when the temperature goes 15 degree Celsius below OT _FAULT_LIMIT.

7.6.2.3.21 OT_WARN_LIMIT (51h)

Format	Linear
Description	The OT_WARN_LIMIT command sets the temperature, in degrees Celsius, at which it should indicate an over-temperature warning condition. The default value is 95C. Upon triggering the over-temperature warning, the following actions are taken: Sets the TEMPERATURE bit in the STATUS_BYTE, Sets the OT Warning bit in the STATUS_TEMPERATURE register, and The device notifies the host (asserts PMB_ALERT).
Default	005Fh

Figure 56. OT_WARN_LIMIT Register

15	14	13	12	11	10	9	8
OTW_WARN_EXPONENT					OTW_WARN_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
OTW_WARN_MANTISSA
R/W

Table 29. OT_WARN_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	OTW_WARN_EXPONENT	R/W	0000 0	—	5-bit, two's complement exponent (scaling factor).
10:0	OTW_WARN_MANTISSA	R/W	000 0101 1111	—	11-bit, two's complement mantissa.

7.6.2.3.22 VIN_OV_FAULT_LIMIT (55h)

Format	Linear
Description	The VIN_OV_FAULT_LIMIT command sets the value of the input voltage that causes an input overvoltage fault condition. The default value is 17 V in NVM mode and 14 V in pinstrap mode. Upon triggering an input voltage fault, the following actions are taken: Sets the OTHER bit in the STATUS_BYTE, Sets the INPUT bit in the upper byte of the STATUS_WORD, Sets the VIN_OV_FAULT bit in the STATUS_INPUT register, and The device notifies the host (asserts PMB_ALERT).
Default	0011h

Figure 57. VIN_OV_FAULT_LIMIT Register

15	14	13	12	11	10	9	8
VIN_OVF_EXPONENT					VIN_OVF_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
VIN_OVF_MANTISSA
R/W

Table 30. VIN_OV_FAULT_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	VIN_OVF_EXPONENT	R/W	0000 0	—	5-bit, two's complement exponent (scaling factor).
10:0	VIN_OVF_MANTISSA	R/W	000 0001 0001	—	11-bit, two's complement mantissa.

After a STORE_DEFAULT_ALL command, the controller reads the last two LSB of VIN_OV_FAULT_LIMIT and convert to decimal, and then adds 14 and converts to save into the VIN_OV_FAULT_LIMIT register. For example, when the two LSB are 01b, after STORE_DEFAULT_ALL command, the VIN_OV_FAULT_LIMIT reads 000Fh (15 V).

7.6.2.3.23 IIN_OC_FAULT_LIMIT (5Bh)

Format	Linear
Description	The IIN_OC_FAULT_LIMIT command sets the value of the input current, in amperes, that the causes an input overcurrent fault condition. Upon triggering the overcurrent fault, the following actions are taken: Sets the OTHER bit in the STATUS_BYTE, Sets the INPUT bit in the STATUS_WORD, Sets the IIN_OC_FAULT bit in the STATUS_INPUT register, and The device notifies the host (asserts PMB_ALERT).
Default	00FFh

Figure 58. IIN_OC_FAULT_LIMIT Register

15	14	13	12	11	10	9	8
INOCF_LIMIT_EXPONENT					INOCF_LIMIT_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
INOCF_LIMIT_MANTISSA
R/W

Table 31. IIN_OC_FAULT_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	INOCF_LIMIT_EXPONENT	R/W	0000 0	—	5-bit, two's complement exponent (scaling factor).
10:0	INOCF_LIMIT_MANTISSA	R/W	000 1111 1111	—	11-bit, two's complement mantissa.

7.6.2.3.24 IIN_OC_FAULT_RESPONSE (5Ch)

Format	N/A
Description	The IIN_OC_FAULT_RESPONSE instructs the device on what action to take in response to an input overcurrent fault. Upon triggering the input overcurrent fault, the controller is latched off, and the following actions are taken: Sets the OTHER bit in the STATUS_BYTE, Sets the INPUT bit in the STATUS_WORD, Sets the IIN_OC_FAULT bit in the STATUS_INPUT register, and The device notifies the host (asserts PMB_ALERT and VR_FAULT).
Default	C0h

Figure 59. IIN_OC_FAULT_RESPONSE Register

7	6	5	4	3	2	1	0
IIN_OC_FAULT_RESPONSE
R-1100 0000

Table 32. IIN_OC_FAULT_RESPONSE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	IIN_OC_FAULT_RESPONSE	R	1100 0000	—	Upon triggering the input overcurrent fault, the device will shut down immediately (disables the output), and will not attempt to restart. The output then remains disabled until the fault is cleared.

7.6.2.3.25 IIN_OC_WARN_LIMIT (5Dh)

Format	Linear
Description	The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes the input overcurrent warning condition. The default setting is 25A. Upon triggering the overcurrent warning, the following actions are taken: Sets the OTHER bit in the STATUS_BYTE, Sets the INPUT bit in the STATUS_WORD, Sets the IIN OC Warning bit in the STATUS_INPUT register, and The device notifies the host (asserts PMB_ALERT).
Default	0019h

Figure 60. IIN_OC_WARN_LIMIT Register

15	14	13	12	11	10	9	8
INOCW_LIMIT_EXPONENT					INOCW_LIMIT_MANTISSA
R/W					R/W

7	6	5	4	3	2	1	0
INOCW_LIMIT_MANTISSA
R/W

Table 33. IIN_OC_WARN_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	INOCW_LIMIT_EXPONENT	R/W	0000 0	—	5-bit, two's complement exponent (scaling factor).
10:0	INOCW_LIMIT_MANTISSA	R/W	000 0001 1001	—	11-bit, two's complement mantissa.

7.6.2.3.26 STATUS_BYTE (78h)

Format	N/A
Description	The STATUS_BYTE command returns a single byte of information with the a summary of critical faults. The STATUS_BYTE command is the same register as the low byte of the STATUS_WORD command. It should be noted that all faults and warnings trigger the assertion of PMB_ALERT.
Default	00h

Figure 61. STATUS_BYTE Register

7	6	5	4	3	2	1	0
BUSY	OFF	VOUT_OV	IOUT_OC	VIN_UV	TEMP	CML	OTHER
R-0	R	R	R	R	R	R	R

Table 34. STATUS_BYTE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	BUSY	R	0	—	Not supported and always set to 0
6	OFF	R		—	This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 0: Raw status indicating the IC is providing power to VOUT. 1: Raw status indicating the IC is not providing power to VOUT.
5	VOUT_OV	R		—	Output Over-Voltage Fault Condition 0: Latched flag indicating no VOUT OV fault has occurred. 1: Latched flag indicating a VOUT OV fault occurred
4	IOUT_OC	R		—	Output Over-Current Fault Condition 0: Latched flag indicating no IOUT OC fault has occurred. 1: Latched flag indicating an IOUT OC fault has occurred.
3	VIN_UV	R		—	Input Under-Voltage Fault Condition 0: Latched flag indicating VIN is above the UVLO threshold. 1: Latched flag indicating VIN is below the UVLO threshold.
2	TEMP	R		—	Over-Temperature Fault/Warning 0: Latched flag indicating no OT fault or warning has occurred. 1: Latched flag indicating an OT fault or warning has occurred.
1	CML	R		—	Communications, Memory or Logic Fault 0: Latched flag indicating no communication, memory, or logic fault has occurred. 1: Latched flag indicating a communication, memory, or logic fault has occurred.
0	OTHER	R		—	Other Fault This bit is used to flag faults not covered with the other bit faults. In this case, UVF or OCW faults are examples of other faults not covered by the bits [6:1] in this register. 0: No fault has occurred 1: A fault or warning not listed in bits [6:1] has occurred.

7.6.2.3.27 STATUS_WORD (79h)

Format	N/A
Description	The STATUS_WORD command returns two bytes of information with a summary of critical faults, such as over-voltage, overcurrent, over-temperature, etc. It should be noted that all faults and warnings except VIN_UV trigger the assertion of PMB_ALERT. NOTE: The STATUS_WORD low byte is the STATUS_BYTE.
Default	0000h

Figure 62. STATUS_WORD Register

15	14	13	12	11	10	9	8
VOUT	IOUT	INPUT	MFR	PGOOD	FANS	OTHER	UNKNOWN
R	R	R	R	R	R-0	R-0	R-0

7	6	5	4	3	2	1	0
BUSY	OFF	VOUT_OV	IOUT_OC	VIN_UV	TEMP	CML	OTHER
R-0	R	R	R	R	R	R	R

Table 35. STATUS_WORD Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15	VOUT	R		—	Output Voltage Fault/Warning 0: Latched flag indicating no VOUT fault or warning has occurred. 1: Latched flag indicating a VOUT fault or warning has occurred.
14	IOUT	R		—	Output Current Fault/Warning 0: Latched flag indicating no IOUT fault or warning has occurred. 1: Latched flag indicating an IOUT fault or warning has occurred.
13	INPUT	R		—	Input Voltage/Current Fault/Warning 0: Latched flag indicating no VIN or IIN fault or warning has occurred. 1: Latched flag indicating a VIN or IIN fault or warning has occurred.
12	MFR	R		—	MFR_SPECIFIC Fault 0: Latched flag indicating no MFR_SPECIFIC fault has occurred. 1: Latched flag indicating a MFR_SPECIFIC fault has occurred.
11	PGOOD	R		—	Power Good Status 0: Raw status indicating VRRDY pin is at logic high. 1: Raw status indicating VRRDY pin is at logic low.
10	FANS	R	0	—	Not supported and always set to 0.
9	OTHER	R	0	—	Not supported and always set to 0.
8	UNKNOWN	R	0	—	Not supported and always set to 0.
7	BUSY	R	0	—	See information in Table 34
6	OFF	R		—
5	VOUT_OV	R		—
4	IOUT_OC	R		—
3	VIN_UV	R		—
2	TEMP	R		—
1	CML	R		—
0	OTHER	R		—

7.6.2.3.28 STATUS_VOUT (7Ah)

Format	N/A
Description	The STATUS_VOUT command returns one byte of information relating to the status of the converter's output voltage related faults.
Default	00h

Figure 63. STATUS_VOUT Register

7	6	5	4	3	2	1	0
VOUT_OVF	VOUT_OVW	VOUT_UVW	VOUT_UVF	VOUT_MAXW	TON_MAX	TOFF_MAX	VOUT_TRACK
R	R-0	R-0	R	R	R-0	R-0	R-0

Table 36. STATUS_VOUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	VOUT_OVF	R		—	Output Over-Voltage Fault 0: Latched flag indicating no VOUT OV fault has occurred. 1: Latched flag indicating a VOUT OV fault has occurred.
6	VOUT_OVW	R	0	—	Not supported and always set to 0.
5	VOUT_UVW	R	0	—	Not supported and always set to 0.
4	VOUT_UVF	R		—	Output Under-Voltage Fault 0: Latched flag indicating no VOUT UV fault has occurred. 1: Latched flag indicating a VOUT UV fault has occurred.
3	VOUT_MAXW	R		—	VOUT Max Warning 0: Latched flag indicating that no VOUT Max warning has occurred 1: Latched flag indicating that an attempt has been made to set the output voltage to a value higher than allowed by the VOUT_MAX command.
2	TON_MAX	R	0	—	Not supported and always set to 0.
1	TOFF_MAX	R	0	—	Not supported and always set to 0.
0	VOUT_TRACK	R	0	—	Not supported and always set to 0.

7.6.2.3.29 STATUS_IOUT (7Bh)

Format	N/A
Description	The STATUS_IOUT command returns one byte of information relating to the status of the converter's output current related faults.
Default	00h

Figure 64. STATUS_IOUT Register

7	6	5	4	3	2	1	0
IOUT_OCF	IOUT_OCUVF	IOUT_OCW	IOUT_UCF	CUR_SHAREF	POW_LIMIT	POUT_OPF	POUT_OPW
R	R-0	R	R-0	R-0	R-0	R-0	R-0

Table 37. STATUS_IOUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	IOUT_OCF	R		—	Output Over-Current Fault 0: Latched flag indicating no IOUT OC fault has occurred. 1: Latched flag indicating a IOUT OC fault has occurred .
6	IOUT_OCUVF	R	0	—	Not supported and always set to 0.
5	IOUT_OCW	R		—	Output Over-Current Warning 0: Latched flag indicating no IOUT OC warning has occurred 1: Latched flag indicating a IOUT OC warning has occurred
4	IOUT_UCF	R	0	—	Not supported and always set to 0.
3	CUR_SHAREF	R	0	—	Not supported and always set to 0.
2	POW_LIMIT	R	0	—	Not supported and always set to 0.
1	POUT_OPF	R	0	—	Not supported and always set to 0.
0	POUT_OPW	R	0	—	Not supported and always set to 0.

7.6.2.3.30 STATUS_INPUT (7Ch)

Format	N/A
Description	The STATUS_INPUT command returns one byte of information relating to the status of the converter's input voltage and current related faults.
Default	00h

Figure 65. STATUS_INPUT Register

7	6	5	4	3	2	1	0
VIN_OVF	VIN_OVW	VIN_UVW	VIN_UVF	VIN_OFF	IIN_OCF	IIN_OCW	PIN_OPW
R	R-0	R-0	R	R-0	R	R	R-0

Table 38. STATUS_INPUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	VIN_OVF	R		—	Input Over-Voltage Fault 0: Latched flag indicating no VIN OV fault has occurred. 1: Latched flag indicating a VIN OV fault has occurred.
6	VIN_OVW	R	0	—	Not supported and always set to 0.
5	VIN_UVW	R	0	—	Not supported and always set to 0.
4	VIN_UVF	R		—	Input Under-Voltage Fault 0: Latched flag indicating no VIN UV fault has occurred. 1: Latched flag indicating a VIN UV fault has occurred.
3	VIN_OFF	R	0	—	Not supported and always set to 0.
2	IIN_OCF	R		—	Input Over-Current Fault 0: Latched flag indicating no IIN OC fault has occurred. 1: Latched flag indicating a IIN OC fault has occurred.
1	IIN_OCW	R		—	Input Over-Current Warning 0: Latched flag indicating no IIN OC warning has occurred. 1: Latched flag indicating a IIN OC warning has occurred.
0	PIN_OPW	R	0	—	Not supported and always set to 0.

7.6.2.3.31 STATUS_TEMPERATURE (7Dh)

Format	N/A
Description	The STATUS_ TEMPERATURE command returns one byte of information relating to the status of the converter's temperature related faults.
Default	00h

Figure 66. STATUS_TEMPERATURE Register

7	6	5	4	3	2	1	0
OTF	OTW	UTW	UTF	Reserved
R	R	R-0	R-0	R-0000

Table 39. STATUS_TEMPERATURE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	OTF	R		—	Over-Temperature Fault 0: Latched flag indicating no temperature fault has occurred. 1: Latched flag indicating a temperature fault has occurred.
6	OTW	R		—	Over-Temperature Warning 0: Latched flag indicating no temperature warning has occurred. 1: Latched flag indicating a temperature warning has occurred.
5	UTW	R	0	—	Not supported and always set to 0.
4	UTF	R	0	—	Not supported and always set to 0.
3-0	Reserved	R	0000	—	Always set to 0.

7.6.2.3.32 STATUS_CML (7Eh)

Format	N/A
Description	The STATUS_ CML command returns one byte with contents regarding communication, logic, or memory conditions.
Default	00h

Figure 67. STATUS_CML Register

7	6	5	4	3	2	1	0
US_CMD	US_DATA	PEC_FAIL	MEM_FAULT	PRO_FAULT	Reserved	COM_FAIL	CML_OTHER
R	R	R	R	R-0	R-0	R	R-0

Table 40. STATUS_CML Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	US_CMD	R		—	Invalid or Unsupported Command Received 0: Latched flag indicating no invalid or unsupported command has received. 1: Latched flag indicating an invalid or unsupported command has received.
6	US_DATA	R		—	Invalid or Unsupported Data Received 0: Latched flag indicating no invalid or unsupported data has received. 1: Latched flag indicating an invalid or unsupported data has received.
5	PEC_FAIL	R		—	Packet Error Check Failed 0: Latched flag indicating no packet error check has failed 1: Latched flag indicating a packet error check has failed
4	MEM_FAULT	R		—	Memory Error 0: Latched flag indicating that there is no memory error. 1: Latched flag indicating that a memory error, i.e. PMBus controller is trying to write into registers when NVM memory is being programmed.
3	PRO_FAULT	R	0	—	Not supported and always set to 0.
2	Reserved	R	0	—	Always set to 0.
1	COM_FAIL	R		—	Other Communication Faults 0: Latched flag indicating no communication fault other than the ones listed in this table has occurred. 1: Latched flag indicating a communication fault other than the ones listed in this table has occurred.
0	CML_OTHER	R	0	—	Not supported and always set to 0.

7.6.2.3.33 STATUS_MFR_SPECIFIC (80h)

Format	N/A
Description	The STATUS_ MFR_SPECIFIC command returns one byte containing manufacturer-specific faults or warnings.
Default	00h

Figure 68. STATUS_MFR_SPECIFIC Register

7	6	5	4	3	2	1	0
MFR_FAULT_PS	MFR_PBF	CUR_SH_WARN			RST_VOUT	VOUT_MIN	PHFLT
R	R	R			R	R	R

Table 41. STATUS_MFR_SPECIFIC Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	MFR_FAULT_PS	R		—	Power State Fault 0: Latched flag indicating no fault from TI power stage has occurred. 1: Latched flag indicating a fault from TI power stage has occurred.
6	MFR_PBF	R		—	Pre-Bias Fault 0: Latched flag indicating no pre-bias fault (V_OUT > 2.75V at startup) has occurred. 1: Latched flag indicating a pre-bias fault (V_OUT > 2.75V at startup) has occurred.
5:3	CUR_SH_WARN	R	000	—	not supported and alwats set to 0
2	RST_VOUT	R		—	RST_VOUT Fault 0: Latched flag indicating no RST_VOUT fault has occurred. 1: Latched flag indicating a RST_VOUT fault has occurred.
1	VOUT_MIN	R		—	VOUT_MIN Fault 0: Latched flag indicating no VOUT_MIN fault has occurred. 1: Latched flag indicating a VOUT_MIN fault has occurred.
0	PHFLT	R		—	Phase Fault 0: Latched flag indicating no phase fault (no phase pulse detected) has occurred. 1: Latched flag indicating a phase fault (no phase pulse detected) has occurred.

7.6.2.3.34 READ_VIN (88h)

Format	Linear
Description	The READ_VIN command returns the input voltage in volts. Refer to Equation 6 to get the real world value.
Default

Figure 69. READ_VIN Register

15	14	13	12	11	10	9	8
READ_VIN_EXPONENT					READ_VIN_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_VIN_MANTISSA
R

Table 42. READ_VIN Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_VIN_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_VIN_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.35 READ_IIN (89h)

Format	Linear
Description	The READ_IIN command returns the input current in amperes. Refer to Equation 6 to get the real world value.
Default

Figure 70. READ_IIN Register

15	14	13	12	11	10	9	8
READ_IIN_EXPONENT					READ_IIN_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_IIN_MANTISSA
R

Table 43. READ_IIN Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_IIN_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_IIN_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.36 READ_VOUT (8Bh)

Format	VID
Description	The READ_VOUT command returns the actual, measured output voltage.
Default

Another command, MFR_READ_VOUT (D4h), returns the measured output voltage in linear format.

Figure 71. READ_VOUT Register

15	14	13	12	11	10	9	8
READ_VOUT_VID
R

7	6	5	4	3	2	1	0
READ_VOUT_VID
R

Table 44. READ_VOUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:0	READ_VOUT_VID	R		—	16-bit, VID format

7.6.2.3.37 READ_IOUT (8Ch)

Format	Linear
Description	The READ_IOUT command returns the output current in amperes. Refer to Equation 6 to get the real world value.
Default

Figure 72. READ_IOUT Register

15	14	13	12	11	10	9	8
READ_IOUT_EXPONENT					READ_IOUT_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_IOUT_MANTISSA
R

Table 45. READ_IOUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_IOUT_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_IOUT_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.38 READ_TEMPERATURE_1 (8Dh)

Format	Linear
Description	The READ_TEMPERATURE_1 command returns the temperature in degrees Celsius. Refer to Equation 6 to get the real world value.
Default

Figure 73. READ_TEMPERATURE_1 Register

15	14	13	12	11	10	9	8
READ_TEMP_1_EXPONENT					READ_TEMP_1_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_TEMP_1_MANTISSA
R

Table 46. READ_TEMPERATURE_1 Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_TEMP_1_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_TEMP_1_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.39 READ_POUT (96h)

Format	Linear
Description	The READ_POUT command returns the output power in watts. Refer to Equation 6 to get the real world value.
Default

Figure 74. READ_POUT Register

15	14	13	12	11	10	9	8
READ_POUT_EXPONENT					READ_POUT_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_POUT_MANTISSA
R

Table 47. READ_POUT Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_POUT_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_POUT_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.40 READ_PIN (97h)

Format	Linear
Description	The READ_PIN command returns the input power in watts. Refer to READ_PIN (97h) to get the real world value.
Default

Figure 75. READ_PIN Register

15	14	13	12	11	10	9	8
READ_PIN_EXPONENT					READ_PIN_MANTISSA
R					R

7	6	5	4	3	2	1	0
READ_PIN_MANTISSA
R

Table 48. READ_PIN Register Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:11	READ_PIN_EXPONENT	R		—	5-bit, two's complement exponent (scaling factor).
10:0	READ_PIN_MANTISSA	R		—	11-bit, two's complement mantissa.

7.6.2.3.41 PMBus_REVISION (98h)

Format	N/A
Description	The PMBus_REVISION command returns the revision of the PMBus to which the device is compliant.
Default	11h

Figure 76. PMBus_REVISION Register

7	6	5	4	3	2	1	0
PMBUS_REV
R-0001 0001

Table 49. PMBus_REVISION Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	PMBUS_REV	R	0001 0001	—	Compliant to revision 1.1 of the PMBus specification.

7.6.2.3.42 MFR_ID (99h)

Format	N/A
Description	The MFR_ID command loads the unit with the text character that contains the manufacturer's ID.
Default	54h

Figure 77. MFR_ID Register

15	14	13	12	11	10	9	8
MFR_ID_BW
R/W

7	6	5	4	3	2	1	0
MFR_ID_HC
R-0000 0001

Table 50. MFR_ID Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	MFR_ID_BW	R/W		Yes	PMBus Block Write
7:0	MFR_ID_HC	R	0000 0001	—	Hard Coded to 01h

7.6.2.3.43 MFR_MODEL (9Ah)

Format	N/A
Description	The MFR_MODEL command loads the unit with the text character that contains the model number of the manufacturer.
Default	NVM:

Figure 78. MFR_MODEL Register

15	14	13	12	11	10	9	8
MFR_MODEL_BW
R/W

7	6	5	4	3	2	1	0
MFR_MODEL_HC
R-0000 0001

Table 51. MFR_MODEL Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	MFR_MODEL_BW	R/W		Yes	PMBus Block Write
7:0	MFR_MODEL_HC	R	0000 0001	—	Hard Coded to 01h

7.6.2.3.44 MFR_REVISION (9Bh)

Format	N/A
Description	The MFR_REVISION command loads the unit with the text character that contains the revision number of the manufacturer. This is typically done once at the time of manufacture.
Default

Figure 79. MFR_REVISION Register

15	14	13	12	11	10	9	8
MFR_REVISION_HC1				MFR_REVISION_BW
R-0000				R/W

7	6	5	4	3	2	1	0
MFR_REVISION_HC2
R-0000 0001

Table 52. MFR_REVISION Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:12	MFR_REVISION _HC1	R	0001	—	Hard Coded to 0h
11:8	MFR_REVISION	R/W		Yes	PMBus Block Write
7:0	MFR_REVISION_HC2	R	0000 0001	—	Hard Coded to 01h

7.6.2.3.45 MFR_DATE (9Dh)

Format	N/A
Description	The MFR_DATE command loads the unit with the text character that identifies the device's date of manufacture. This is typically done once at the time of manufacture.
Default

Figure 80. MFR_DATE Register

15	14	13	12	11	10	9	8
MFR_DATE_BW
R/W

7	6	5	4	3	2	1	0
MFR_DATE_HC
R-0000 0001

Table 53. MFR_DATE Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	MFR_DATE_BW	R/W		Yes	PMBus Block Write
7:0	MFR_DATE_HC	R	0000 0001	—	Hard Coded to 01h.

7.6.2.3.46 MFR_VOUT_MIN (A4h)

Format	VID
Description	The MFR_VOUT_MIN command sets an lower limit on the output voltage that the unit can command regardless of any other commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output voltage to a possibly non-operational level. The device detects that an attempt has been made to program the output to a voltage lower than the value set by the MFR_VOUT_MIN command. The device treats this detection as a warning condition and not a fault condition. If an attempt is made to program the output voltage lower than the limit set by this command, the device responds as follows: The commanded output voltage is set to MFR_VOUT_MIN, The OTHER bit is set in the STATUS_BYTE, The VOUT bit is set in the STATUS_WORD, The MFR_VOUT_MIN warning bit is set in the STATUS_VOUT register, and The device notifies the host (asserts PMBUS_ALERT). The data bytes are two bytes, which are in right-justified VID format. The VID table mapping determined by the selected VID protocols (VR12.0 or VR12.5) from the SLEW_MODE pin or MFR_SPECIFIC_13.
Default	0000h

Figure 81. MFR_VOUT_MIN Register

15	14	13	12	11	10	9	8
RESERVED
R-0000 0000

7	6	5	4	3	2	1	0
MFR_VOUT_MIN
R/W

Table 54. MFR_VOUT_MIN Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	RESERVED	R	0000 0000	—	Hard coded to 00h
7:0	MFR_VOUT_MIN	R/W	0000 0000	—	Minimum value for VID

7.6.2.3.47 MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) (D0h)

Format	N/A
Description	The MFR_SPECIFIC_00 command sets the valley-current threshold for the per-phase overcurrent limit. The settings can override the default setting form the OCL-R pin.
Default	Pin strap: OCL-R pin NVM: 08h

Figure 82. MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) Register

7	6	5	4	3	2	1	0
Reserved				OCL
R-0000				R/W

Table 55. MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:4	Reserved	R	R-0000	—	Always set to 0.
3:0	OCL	R/W		Yes	0000: 24A 0001: 27A 0010: 30A 0011: 33A 0100: 36A 0101: 39A 0110: 42A 0111: 45A 1000: 48A 1001: 51A 1010: 54A 1011: 57A 1100: 60A 1101: 63A 1110: 66A 1111:69A

7.6.2.3.48 MFR_SPECIFIC_01 (Telemetry Averaging Time) (D1h)

Format
Description	The MFR_SPECIFIC_01 command sets the averaging time for telemetry reporting.
Default	50h

Figure 83. MFR_SPECIFIC_01 (Telemetry Averaging Time) Register

7	6	5	4	3	2	1	0
Reserved	FILTER_PIN			Reserved		FILTER_IV
R-0	R/W			R-00		R/W

Table 56. MFR_SPECIFIC_01 (Telemetry Averaging Time) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	Reserved	R	0	—	Always set to 0.
6:4	FILTER_PIN	R/W	101	—	Averaging Time for Input Power Reporting 000: Bypass. 001: 2 ms 010: 5.5 m 011: 11.5 m 100: 19 ms 101: 50 ms 110: 100 ms 111: 225 ms
3:2	Reserved	R	00	—	Always set to 0.
1:0	FILTER_IV	R/W	00	—	Averaging Time for Current and Voltage Reporting 00: Bypass. 01: .5 ms 10: 1 ms 11: 2.5 ms

7.6.2.3.49 MFR_SPECIFIC_04 (Read VOUT) (D4h)

Format	Linear
Description	The MFR_SPECIFIC_04 command returns the actual, measured output voltage in volts. Refer to Equation 6 to get the real world value, where n= -9.
Default

Figure 84. MFR_SPECIFIC_04 (Read VOUT) Register

15	14	13	12	11	10	9	8
MFR_SPEC_04_MANTISSA
R

7	6	5	4	3	2	1	0
MFR_SPEC_04_MANTISSA
R

Table 57. MFR_SPECIFIC_04 (Read VOUT) Register Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:0	MFR_SPEC_04_MANTISSA	R		—	Unsigned 16-bit mantissa with an exponent value of n=-9.

7.6.2.3.50 MFR_SPECIFIC_05 (VOUT Trim) (D5h)

Format	Signed Two's Complement
Description	The MFR_SPECIFIC_05 command is used to trim the VR output voltage in volts. LSB resolution is 5 mV/10 mV based on the selected VR12.0/VR12.5.
Default	NVM: 00h

Figure 85. MFR_SPECIFIC_05 (VOUT Trim) Register

7	6	5	4	3	2	1	0
VOUT_VID_OFFSET
R/W

Table 58. MFR_SPECIFIC_05 (VOUT Trim) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	VOUT_VID_OFFSET	R/W		Yes	Sets the VR output trim voltage. 01111111: 0.635 V in VR12.0 and 1.27V in VR12.5 01111110: 0.630 V in VR12.0 and 1.26 V in VR12.5 ........................... 00000001: 0.005 V in VR12.0 and 0.01 V in VR12.5 00000000: 0 V 11111111: –0.005 V in VR12.0 and –0.01 V in VR12.5 ........................... 10000001: –0.635 V in VR12.0 and –1.27 V in VR12.5 10000000: –0.640 V in VR12.0 and –1.28 V in VR12.5

7.6.2.3.51 MFR_SPECIFIC_07 (Additional Function Bits) (D7h)

Format	N/A
Description	The MFR_SPECIFIC_07 command sets the additional function bits.
Default	NVM: 02h

Figure 86. MFR_SPECIFIC_07 (Additional Function Bits) Register

7	6	5	4	3	2	1	0
Reserved			OVFLT_MODE_SEL	PS_FLT_DIS	SLEW_FAST	OSR_TRISTATE	SST_TIME
R-0000 0					R/W

Table 59. MFR_SPECIFIC_07 (Additional Function Bits) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:5	Reserved	R	000	—	Always set to 0.
4	OVFLT_MODE_SEL	R/W		No	0: Tracking OVP and Fixed OVP is 3 cycle hiccup then latch off 1: Tracking OVP and Fixed OVP is latch off from first occurrence.
3	PS_FLT_DIS	R/W		No	0: Power stage fault is active 1: Power stage fault is disabled
2	SLEW_FAST	R/W		Yes	Fast Slew Mode Enable/Disable 0: Default slew rate selected by MFR_SPECIFIC_13[2:0] 1: Add 1.36 mV/µs to the selected slew rate
1	OSR_TRISTATE	R/W		Yes	Body Braking Enable/Disable 0: Enable OSR pulse truncation without body braking 1: Enable OSR pulse truncation with body braking
0	SST_TIME	R/W		Yes	Soft Slew Rate Selection 0: soft start slew rate dependent on TRISE 1: 1/16 of the selected slew rate for soft-start

7.6.2.3.52 MFR_SPECIFIC_08 (Droop) (D8h)

Format	N/A
Description	The MFR_SPECIFIC_08 command sets the load line as percentage of the default one. For example, if slope is set as 1mohm = 100%, then 0.5mohm = 50%
Default	04h

Figure 87. MFR_SPECIFIC_08 (Droop) Register

7	6	5	4	3	2	1	0
DROOP
R/W

Table 60. MFR_SPECIFIC_08 (Droop) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	DROOP	R/W	0000 0100	—	0000 0000: 0% 0000 0001: 25% 0000 0010: 50% 0000 0011: 75% 0000 0100: 100% 0001 0000: 80% 0010 0000: 85% 0011 0000: 90% 0100 0000: 95% 0101 0000: 105% 0110 0000: 110% 0111 0000: 115% 1000 0000: 120% 1001 0000: 125% 1010 0000: 150% 1011 0000: 175% Others: 100%

7.6.2.3.53 MFR_SPECIFIC_09 (OSR/USR) (D9h)

Format	N/A
Description	The MFR_SPECIFIC_09 command sets the threshold for OSR and USR control. The setting can override the default setting from the O-USR pin.
Default	Pin strap: O-USR pin NVM: 77h

Figure 88. MFR_SPECIFIC_09 (OSR/USR) Register

7	6	5	4	3	2	1	0
Reserved	USR			Reserved	OSR
R-0	R/W			R-0	R/W

Table 61. MFR_SPECIFIC_09 (OSR/USR) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7	Reserved	R	0	—	Always set to 0.
6:4	USR	R/W		Yes	Undershoot Reduction 000: 20 mV 001: 30 mV 010: 60 mV 011: 80 mV 100: 100 mV 101: 120 mV 110: 140 mV 111: USR off
3	Reserved	R	0	—	Always set to 0.
2:0	OSR	R/W		Yes	Overshoot Reduction 000: 30 mV 001: 40 mV 010: 60 mV 011: 80 mV 100: 100 mV 101: 120 mV 110: 140 mV 111: OSR off

7.6.2.3.54 MFR_SPECIFIC_10 (Maximum Operating Current) (DAh)

Format	N/A
Description	The MFR_SPECIFIC_10 command sets the maximum operating current (IMAX, unit: A) of the converter. The setting can override the default setting from the F-IMAX pin
Default	Pin strap: F-IMAX pin NVM:

Figure 89. MFR_SPECIFIC_10 (Maximum Operating Current) Register

7	6	5	4	3	2	1	0
IMAX
R/W

Table 62. MFR_SPECIFIC_10 (Maximum Operating Current) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	IMAX	R/W		Yes	Set maximum operating current.

7.6.2.3.55 MFR_SPECIFIC_11 (VBOOT) (DBh)

Format	VID
Description	The MFR_SPECIFIC_11 command sets the boot voltage in 8-bit VID format. The setting can override the default setting from the VBOOT pin.
Default	Pin strap: VBOOT pin NVM: 97h

Figure 90. MFR_SPECIFIC_11 (VBOOT) Register

7	6	5	4	3	2	1	0
VBOOT
R/W

Table 63. MFR_SPECIFIC_11 (VBOOT) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:0	VBOOT	R/W		Yes	Set the boot voltage according to the selected VID table.

7.6.2.3.56 MFR_SPECIFIC_12 (Switching Frequency and TRISE) (DCh)

Format	N/A
Description	The MFR_SPECIFIC_12 command sets the switching frequency and the soft start rise slew rate. The settings can override the default setting from the F-IMAX.
Default	Pin strap: F-IMAX pin NVM: 20h

Figure 91. MFR_SPECIFIC_12 (Switching Frequency and TRISE) Register

7	6	5	4	3	2	1	0
FSW				Reserved		TRISE
R/W				R-0		R/W

Table 64. MFR_SPECIFIC_12 (Switching Frequency and TRISE) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:4	FSW	R/W		Yes	Switching Frequency 0000: 300 kHz 0001: 400 kHz 0010: 500 kHz 0011: 600 kHz 0100: 700 kHz 0101: 800 kHz 0110: 900 kHz 0111: 1000 kHz 1000: 350 kHz 1001: 450 kHz 1010: 550 kHz 1011: 650 kHz 1100: 750 kHz 1101: 850 kHz 1110: 950 kHz 1111: 1000 kHz
3:2	Reserved	R	0	—	Always set to 0.
1:0	TRISE	R/W		Yes	Soft start rise slew rate in terms of VOUT slew rate 00: 1 01: 1/2 10: 1/4 11: 1/8

7.6.2.3.57 MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) (DDh)

Format	N/A
Description	The MFR_SPECIFIC_13 command sets the slew rates and the operation modes. The settings can override the default setting from the SLEW-MODE pin.
Default	Pin strap: SLEW-MODE pin NVM: 89h

Figure 92. MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) Register

7	6	5	4	3	2	1	0
VR12_MODE	PI_SET	Reserved	DPS_EN	ZLL_SET	SLEW
R/W	R/W	R/W	R/W	R/W	R/W

Table 65. MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) Register Field Descriptions

Bit	Field	Type	NVM	Description
7	VR12_MODE	R/W	Yes	VR12 Mode 0: VR12.5. 1: VR12.0.
6	PI_SET	R/W	Yes	Phase Interleaving 0: 1: 1/3, 2/4 and 5/6 phase interleaving
5	Reserved	R/W	Yes	Not used, write or read has no effect
4	DPS_EN	R/W	Yes	Dynamic Phase Shedding Enable 0: Disable dynamic phase shedding. 1: Enable dynamic phase shedding.
3	ZLL_SET	R/W	Yes	Load Line 0: Non-zero load line 1: Zero load line
2:0	SLEW	R/W	Yes	Slew Rate 000: 0.34 mV/µs 001: 0.68 mV/µs 010: 1.02 mV/µs 011: 1.36 mV/µs 100: 1.7 mV/µs 101: 2.04 mV/µs 110: 2.38 mV/µs 111: 2.74 mV/µs

7.6.2.3.58 MFR_SPECIFIC_14 (Ramp Height) (DEh)

Format	N/A
Description	The MFR_SPECIFIC_14 command sets the ramp amplitude for compensations. The settings can override the default setting from the OCL-R pin.
Default	Pin strap: OCL-R pin NVM: 06h

Figure 93. MFR_SPECIFIC_14 Register

7	6	5	4	3	2	1	0
Reserved					RAMP
R-0000 0					R/W

Table 66. MFR_SPECIFIC_14 Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:3	Reserved	R	0	—	Always set to 0.
2:0	RAMP	R/W		Yes	Ramp Amplitude 000: 20 mV_PP 001: 40 mV_PP 010: 60 mV_PP 011: 80 mV_PP 100: 100 mV_PP 101: 120 mV_PP 110: 150 mV_PP 111: 200 mV_PP

7.6.2.3.59 MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh)

Format	N/A
Description	The MFR_SPECIFIC_15 command sets the threshold for the dynamic phase shedding. Use 4 × overcurrent limit (OCL) as 100% load condition
Default	NVM: 01h

Figure 94. MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) Register

7	6	5	4	3	2	1	0
Reserved				DPS_TH_LOW	DPS_TH_HIGH
R-0000				R/W	R/W

Table 67. MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:4	Reserved	R	0000	—	Always set to 0.
3	DPS_TH_LOW	R/W		Yes	Switch from 2 Phase to 1 Phase Operation 0: Disable decreasing to 1 phase operation. 1: 10% load.
2:0	DPS_TH_HIGH	R/W		Yes	Switch from 6 Phase to 2 Phase Operation 000: 15% load. 001: 20% load. 010: 25% load. 011: 30% load. Others: 35% load.

7.6.2.3.60 MFR_SPECIFIC_16 (VIN UVLO) (E0h)

Format	N/A
Description	The MFR_SPECIFIC_16 command sets the threshold for the VIN Undervoltage Lockout (UVLO).
Default	NVM: 01h

Figure 95. MFR_SPECIFIC_16 (VIN UVLO) Register

7	6	5	4	3	2	1	0
Reserved						VIN_UVLO
R-00 0000						R/W

Table 68. MFR_SPECIFIC_16 (VIN UVLO) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:2	Reserved	R	00 0000	—	Always set to 0.
1:0	VIN_UVLO	R/W	01	Yes	Input Voltage UVLO 00:4.25V 01: 6.0V 10: 8.1V 11: 10.2V

7.6.2.3.61 MFR_SPECIFIC_19 (E3h)

Format	N/A
Description	The MFR_SPECIFIC_19 command sets the thresholds for determining the current sharing warning. Once the difference between any phase current and the average current is larger than the pre-defined threshold, the STATUS_IOUT [3] will be set while asserting PMB_ALERT#.
Default	0003h

Figure 96. MFR_SPECIFIC_19 Register

15	14	13	12	11	10	9	8
Reserved
R- 0000 0000

7	6	5	4	3	2	1	0
PHFLT_DIS_SEL	Reserved				CUR_SHARE_TH
R/W	R- 0000				R/W

Table 69. MFR_SPECIFIC_19 Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	__	Always set to 0.
7	PHFLT_DIS_SEL	R/W	0	Yes	0: Phase with Current Share Warning will be turned off. 1: Phase with Current Share Warning will NOT be turned off.
6:3	Reserved	R	0000	—	Always set to 0.
2:0	CUR_SHARE_TH	R/W	011	Yes	000: 2 Amps 001: 4 Amps 010: 6 Amps 011: 8 Amps 000: 10 Amps 001: 15 Amps 010: 20 Amps 011: OFF

7.6.2.3.62 MFR_SPECIFIC_20 (Maximum Operational Phase Number) (E4h)

Format	N/A
Description	The MFR_SPECIFIC_20 command sets the maximum operational phase numbers on-the-fly. If the maximum operational phase number is set higher than the available phase numbers specified by hardware, then the operational phase number remains unchanged, and the STAUTS_MFR_SPECIFIC<3> is set while asserting PMB_ALERT.
Default	Hardware Specific

Figure 97. MFR_SPECIFIC_20 (Maximum Operational Phase Number) Register

7	6	5	4	3	2	1	0
Reserved					PHASE_NUM
R-0 0000					R/W

Table 70. MFR_SPECIFIC_20 (Maximum Operational Phase Number) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:3	Reserved	R	0 0000	—	Always set to 0.
2:0	PHASE_NUM	R/W		—	Phase Number 000: 1-phase operation. 001: 2-phase operation. 010: 3-phase operation. 011: 4-phase operation. 100: 5-phase operation. 101: 6-phase operation. Others: Not allowed

7.6.2.3.63 MFR_SPECIFIC_21 (VIN UVLO) (E5h)

Format	N/A
Description	The MFR_SPECIFIC_21 command programs the over-voltage thresholds. Tracking OV threshold: VOUT_COMMAND + OV_TRACK_OFFSET Fixed OV threshold: VOUT_MAX + FIX_OV_OFFSET
Default	0Fh

Figure 98. MFR_SPECIFIC_21 Register

7	6	5	4	3	2	1	0
Reserved			OV_TRACK_OFFSET		FI_OV_OFFSET
R-000			R/W		R/W

Table 71. MFR_SPECIFIC_21 Register Field Descriptions

Bit

Field

Type

Reset

NVM

Description

7:5

Reserved

000

—

Always set to 0.

4:3

OV_TRACK_OFFSET

Yes

00:175mV

01:225mV

10:275mV

11:325 mV

2:0

FIX_OV_OFFSET

Yes

000: 50mV

001: 100mV

010: 150mV

011: 200mV

100: 250mV

101: 300mV

110: 350mV

111: 400mV

7.6.2.3.64 MFR_SPECIFIC_22 ( VOUT_UV_FAULT_threshold) (E6h)

Format	N/A
Description	The MFR_SPECIFIC_22 command sets the value of VOUT undervoltage threshold. UVP threshold = VOUT_COMMAND - Load Line * Iout - VOUT_UVF_OFFSET
Default	NVM: 03h

Figure 99. MFR_SPECIFIC_22 (VOUT_UV_FAULT_threshold) Register

7	6	5	4	3	2	1	0
Reserved					VOUT_UVF_THRESHOLD
R-0 0000					R/W

Table 72. MFR_SPECIFIC_22 (VOUT_UV_FAULT_threshold) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:3	Reserved	R	0 0000	—	Always set to 0.
2:0	VOUT_UVF_OFFSET	R/W		Yes	VOUT UVF threshold 000: 50 mV 001: 100 mV 010: 150 mV 011: 200 mV 100: 250 mV 101: 300 mV 110: 325 mV 111: 400 mV

7.6.2.3.65 MFR_SPECIFIC_23 (E7h)

Format	N/A
Description	The MFR_SPECIFIC_23 command sets the boot voltage in 8-bit VID format. (Same as MFR_SPECIFIC_11) The two data bytes contain of a right-justified VID code with VID0 in bit 0 of the lower data byte, VID1 in bit 1 of the lower byte and so forth.
Default

Figure 100. MFR_SPECIFIC_23 Register

15	14	13	12	11	10	9	8
Reserved
R- 0000 0000

7	6	5	4	3	2	1	0
BOOT_CODE
R/W

Table 73. MFR_SPECIFIC_23 Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:8	Reserved	R	0000 0000	__	Always set to 0.
7:0	BOOT_CODE	R/W		Yes	Set the boot voltage according to the selected VID table.

7.6.2.3.66 MFR_SPECIFIC_24 (E8h)

Format	N/A
Description	The MFR_SPECIFIC_24 command set is used to enable/disable the Phases in Analog along with some other settings/logic.
Default

Figure 101. MFR_SPECIFIC_24 (VIN UVLO) Register

7	6	5	4	3	2	1	0
Reserved		PH5_DIS	PH4_DIS	PH3_DIS	PH2_DIS	PH1_DIS	PH0_DIS
R-00		R/W

Table 74. MFR_SPECIFIC_24 (VIN UVLO) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
7:6	Reserved	R	00	—	Always set to 0.
5	PH5_DIS	R/W	0	No	1: Phase5 is disabled. 0: Phase5 is not disabled.
4	PH4_DIS	R/W	0	No	1: Phase4 is disabled. 0: Phase4 is not disabled.
3	PH3_DIS	R/W	0	No	1: Phase3 is disabled. 0: Phase3 is not disabled.
2	PH2_DIS	R/W	0	No	1: Phase2 is disabled. 0: Phase2 is not disabled.
1	PH1_DIS	R/W	0	No	1: Phase1 is disabled. 0: Phase1 is not disabled.
0	PH0_DIS	R/W	0	No	1: Phase0 is disabled. 0: Phase0 is not disabled.

7.6.2.3.67 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)

Format
Description	The MFR_SPECIFIC_44 command reads back the DEVICE_CODE information.
Default	01F8h

Figure 102. MFR_SPECIFIC_44 (DEVICE_CODE) Register

15	14	13	12	11	10	9	8
DEVICE_CODE
R-0000 0001

7	6	5	4	3	2	1	0
DEVICE_CODE
R-1111 0000

Table 75. MFR_SPECIFIC_44 (DEVICE_CODE) Register Field Descriptions

Bit	Field	Type	Reset	NVM	Description
15:0	DEVICE_CODE	R	0000 0001 1111 0000	—	Device Code