10.1 Layout Guidelines

Layout is a critical portion of good power supply design. Several signals paths conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Figure 64 shows the PCB layout example. Obtaining acceptable performance with alternate PCB layouts may be possible, however this layout has been shown to produce good results and is meant as a guideline.

The following layout guidelines should be followed to achieve good system performance:

• Providing a low-inductance, low-impedance ground path is critical. Therefore, use wide and short traces for the main current paths.
• Care should be taken to minimize the loop area formed by the input bypass capacitor, VIN pin, PH pin, catch diode, inductor, and output capacitors. Use thick planes and traces to connect these components. For operation at a full-rated load, the top-side ground area must provide adequate heat dissipating area.
• The GND pin should be tied directly to the thermal pad under the device and the thermal pad.
• The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under the device.
• The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
• Place the VSENSE voltage-divider resistor network away from switching node and route the feedback trace with minimum interaction with any noise sources associated with the switching components.
• The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the device and should be routed with minimal lengths of trace.
• Place compensation network components away from switching components and route the connections away from noisy area.
• The bootstrap capacitor must be placed as close as possible to the IC pin.

10.2 Layout Example

Figure 64. PCB Layout Example

10.3 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).

The power dissipation of the device includes the parameters that follow:

• Conduction loss (Pcon)
Equation 49.
where
• R_DS(on) is the on-resistance of the high-side MOSFET (Ω).
• VOUT is the output voltage (V).
• VIN is the input voltage (V).
• Switching loss (Psw)
Equation 50.
where
• fsw is the switching frequency (Hz).
• Io is the output current (A).
• Gate drive loss (Pgd)
Equation 51.
• Supply current (Pq)
Equation 52.

Therefore:

Equation 53.

where

• Ptot is the total device power dissipation (W).

For given TA:

Equation 54.

where

• TJ is the junction temperature (°C).
• TA is the ambient temperature (°C).
• Rth is the thermal resistance of the package (°C/W).

For given TJ_MAX = 150°C:

Equation 55.

where

• TJmax is maximum junction temperature (°C).
• TAmax is maximum ambient temperature (°C).

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode, and trace resistance which impact the overall efficiency of the regulator.