SLUSCZ1 May 2017 TPS92518-Q1
PRODUCTION DATA.
CONTROL is shown in Figure 38 and described in Table 3.
Return to Summary Table.
8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THERM
SMPL EN |
VLED2
SMPL EN |
VLED1
SMPL EN |
LED2
EN |
LED1
EN |
|||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
8-5 | RESERVED | R | 0 |
Reserved |
4 | THERM_SMPL_EN | R/W | 0 |
Thermal sample enable 0 = Disable sampling 1 = Enable sampling |
3 | VLED2_SMPL_EN | R/W | 0 |
VLED2 sample enable 0 = Disable sampling 1 = Enable sampling |
2 | VLED1_SMPL_EN | R/W | 0 |
VLED1 sample enable 0 = Disable sampling 1 = Enable sampling |
1 | LED2_EN | R/W | 0 |
LED2 enable. This bit controls the operation state of channel 2. 0 = Disable LED channel 2 1 = Enable LED channel 2 |
0 | LED1_EN | R/W | 0 |
LED1 enable. This bit controls the operation state of channel 1. 0 = Disable LED channel 1 1 = Enable LED channel 1 |
xSMPL_EN: The TPS92518-Q1 Analog to Digital Converter (ADC) input is multiplexed between 3 inputs: the thermal sensor and the two output voltages. Each input is sampled consecutively. Sampling a single input increases the sampling frequency. For example: an ADC sample and conversion requires ~100us. If one item is selected it is sampled at roughly 10 kHz. If all three inputs are selected each is sampled at ~3.3 kHz.
LEDx_EN: The TPS92518-Q1 PWMx pin AND the corresponding LEDxEN bit must be high for a channel to be enabled. If not using the external PWM input, tie the pin to VCC. The use of the LEDxEN register also enables the corresponding channel SWx pin internal pull-down to ensure no current flows to the LED load. A sample of the timing and waveforms around a SPI enable write are shown in Figure 39.
LEDxEN control may be bypassed using an analog activated override via the EN/UV pin. By applying a voltage >VEN/UV2 (23.6 V Typical) the contents of LEDxEN are ignored and the TPS92518-Q1 operates without SPI communication using the default register values. This is discussed in EN/UV2 - SPI Control Bypass