JAJSHS0C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
SWDIV register holds the divider value associated with dividing down the main clock to generate the channel clocks (switching frequency fSW).
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
03h | SWDIV | RSVD | RSVD | RSVD | RSVD | CH2DIV1:0 | CH1DIV1:0 | 00000000 |
00: Division = 2. CHxCLK = fCLKM / 2
01: Division = 4. CHxCLK = fCLKM / 4
10: Division = 8. CHxCLK = fCLKM / 8
11: Division = 8. CHxCLK = fCLKM / 8