JAJSE97D June 2017 – May 2019 DAC8740H , DAC8741H
PRODUCTION DATA.
Table 7 lists the memory-mapped registers for the DAC8741H. All register offset addresses not listed in Table 7 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
2h | CONTROL | CONTROL register | Go |
7h | RESET | RESET register | Go |
20h | MODEM_STATUS | MODEM STATUS register | Go |
21h | MODEM_IRQ_MASK | MODEM IRQ MASK register | Go |
22h | MODEM_CONTROL | MODEM CONTROL register | Go |
23h | FIFO_D2M | FIFO D2M register | Go |
24h | FIFO_M2D | FIFO M2D register | Go |
25h | FIFO_LEVEL_SET | FIFO LEVEL SET register | Go |
27h | PAFF_JABBER | PAFF JABBER register | Go |
Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |