SLAZ312AD October 2012 – May 2021 MSP430F5527
USB Module
Functional
Endpoint0 STALL bit can be cleared during USBIEPCNFG_0/ USBOEPCNFG_0 register access
According to the MSP430F5xx Family User's Guide (SLAU208), the STALL bit in the Endpoint0 configuration register should be set by software when there is either an unsupported control request or a control request fail or an endpoint halt, and this bit is automatically cleared by the next setup transaction. In correct operation, the hardware clearing of the Endpoint0 STALL bit should not occur when the configuration registers USBIEPCNFG_0/USBOEPCNFG_0 are being accessed even though the next set-up transaction required to clear the STALL bit has occurred. Rather, the hardware clear of the STALL bit should wait until the access is finished, and then clear the bit.
However due to the erratum, if the next setup transaction occurs while the USBIEPCNFG_0/USBOEPCNFG_0 registers are being accessed, the STALL bit will be cleared immediately. This can be a problem during write accesses; for example, if the application tries to set the STALL bit and the next set-up transaction has cleared it. In this case, a valid STALL condition might be missed.
- Set the STALL bit inside the SETUP ISR. The STALL bit is automatically cleared on entering SETUP ISR so the user does not need to check it is cleared before setting STALL = 1.
or
- Poll the STALL bit to verify it is cleared, then set STALL = 1.
NOTE: The USB stacks supplied by TI implement the first software workaround.