SPRZ398J November 2012 – February 2021 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
DELAYMODE Mechanism Not Selecting Proper Delay for Some IP Modes
High
IO timings are not met for some IPs and IP modes, and specific configuration of the DELAYMODE and SLEW configurations in the pad control registers (control module) are required for them.
If these modes are used, the SoC should only be used under nominal conditions (for example, room temp/lab/software development), not for production testing.
SR 1.0
TDA2x: 1.0
DRA75x, DRA74x: 1.0
AM572x: 1.0