SPRZ572A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
GPIO: 5V Signal Cannot Drive Low When 20mA Drive Mode is Enabled for Select GPIOs
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GPIOs 2, 3, 9, and 32 have support for 5V level TTL signals, and also have a selectable drive strength (either 4mA or 20mA) in order to enable fast plus mode for PMBUS communications. This is controlled with the DRIVESEL bit in the IO_DRVSEL register in the analog subsystem module. If the voltage on the GPIO pin is above VDDIO + 0.3V and the DRIVESEL bit = 1, then the GPIO will not be able to drive the pin to a logical low.
If the voltage level on the GPIOs in question is kept to VDDIO + 0.3V or below, there is no impact to the functional behavior of the device. If voltage levels at the pin are above VDDIO + 0.3V, then the DRIVESEL bit should be set to "0", disabling the higher drive strength to the GPIO. In this scenario, fast plus mode is no longer supported; and the max clock rate of the PMBUS is 400kHz, supporting fast mode only.