SPRZ572A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6. 3.2.1 Advisory
      7.      Advisory
      8. 3.2.2 Advisory
      9.      Advisory
      10. 3.2.3 Advisory
      11.      Advisory
      12.      Advisory
      13. 3.2.4 Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5. 4.2.1 Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

ADC: There is a Resistive Path Between the Shared Analog Inputs Present on the VREFHI/VREFLO Pins

Revisions Affected

0

Details

When the ADC reference is set to VDDA/VSSA, the VREFHI and VREFLO pins may be used as additional input channels to the ADCs on the device. The VREFHI pin is shared with ADC inputs D20 and E20 channels; and the VREFLO pin is shared with ADC inputs A13, B13, C13, D1, and E13. In this reference mode, there is a resistive connection between these two pins.

Workaround

There is no issue if the VREFHI and VREFLO pins are used for the analog reference. If the pins are used as analog inputs it is recommended to only drive one of the two, and float the other.