SPRZ572A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
ADC: Degraded ADC Performance With ADCCLK Fractional Divider
0, A
Using fractional SYSCLK-to-ADCCLK dividers (controlled by the ADCCTL2.PRESCALE field) has been shown to cause degradation in ADC performance on this device. See Table 3-1.
REDUCED PERFORMANCE | |||
---|---|---|---|
BIT | FIELD | VALUE | DESCRIPTION |
3–0 | PRESCALE | 0001 | ADCCLK = SYSCLK/1.5 |
0003 | ADCCLK = SYSCLK/2.5 | ||
... | |||
NORMAL PERFORMANCE | |||
BIT | FIELD | VALUE | DESCRIPTION |
3–0 | PRESCALE | 0000 | ADCCLK = SYSCLK/1.0 |
0002 | ADCCLK = SYSCLK/2.0 | ||
... |
Use even PRESCALE clock divider values. Even PRESCALE values result in integer clock dividers which do not impact the ADC performance.