JAJSFK6E October   2019  – October 2019 TAS5825M

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. 概要 (続き)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
      1. 8.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 8.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 8.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 8.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Power Supplies
      2. 10.3.2 Device Clocking
      3. 10.3.3 Serial Audio Port – Clock Rates
      4. 10.3.4 Clock Halt Auto-recovery
      5. 10.3.5 Sample Rate on the Fly Change
      6. 10.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 10.3.7 Digital Audio Processing
      8. 10.3.8 Class D Audio Amplifier
        1. 10.3.8.1 Speaker Amplifier Gain Select
        2. 10.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 10.4 Device Functional Modes
      1. 10.4.1 Software Control
      2. 10.4.2 Speaker Amplifier Operating Modes
        1. 10.4.2.1 BTL Mode
        2. 10.4.2.2 PBTL Mode
      3. 10.4.3 Low EMI Modes
        1. 10.4.3.1 Spread Spectrum
        2. 10.4.3.2 Channel to Channel Phase Shift
        3. 10.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 10.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 10.4.3.3.2 Phase Synchronization With GPIO
      4. 10.4.4 Thermal Foldback
      5. 10.4.5 Device State Control
      6. 10.4.6 Device Modulation
        1. 10.4.6.1 BD Modulation
        2. 10.4.6.2 1SPW Modulation
        3. 10.4.6.3 Hybrid Modulation
    5. 10.5 Programming and Control
      1. 10.5.1 I2 C Serial Communication Bus
      2. 10.5.2 I2 C Slave Address
        1. 10.5.2.1 Random Write
        2. 10.5.2.2 Sequential Write
        3. 10.5.2.3 Random Read
        4. 10.5.2.4 Sequential Read
        5. 10.5.2.5 DSP Memory Book, Page and BQ update
        6. 10.5.2.6 Checksum
          1. 10.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 10.5.2.6.2 Exclusive or (XOR) Checksum
      3. 10.5.3 Control via Software
        1. 10.5.3.1 Startup Procedures
        2. 10.5.3.2 Shutdown Procedures
        3. 10.5.3.3 Protection and Monitoring
          1. 10.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 10.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 10.5.3.3.3 DC Detect
    6. 10.6 Register Maps
      1. 10.6.1 CONTROL PORT Registers
        1. 10.6.1.1  RESET_CTRL Register (Offset = 1h) [reset = 0x00]
          1. Table 8. RESET_CTRL Register Field Descriptions
        2. 10.6.1.2  DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
          1. Table 9. DEVICE_CTRL_1 Register Field Descriptions
        3. 10.6.1.3  DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]
          1. Table 10. DEVICE_CTRL2 Register Field Descriptions
        4. 10.6.1.4  I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
          1. Table 11. I2C_PAGE_AUTO_INC Register Field Descriptions
        5. 10.6.1.5  SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
          1. Table 12. SIG_CH_CTRL Register Field Descriptions
        6. 10.6.1.6  CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
          1. Table 13. CLOCK_DET_CTRL Register Field Descriptions
        7. 10.6.1.7  SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
          1. Table 14. SDOUT_SEL Register Field Descriptions
        8. 10.6.1.8  I2S_CTRL Register (Offset = 31h) [reset = 0x00]
          1. Table 15. I2S_CTRL Register Field Descriptions
        9. 10.6.1.9  SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
          1. Table 16. SAP_CTRL1 Register Field Descriptions
        10. 10.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
          1. Table 17. SAP_CTRL2 Register Field Descriptions
        11. 10.6.1.11 SAP_CTRL3 Register (Offset = 35h) [reset = 0x11]
          1. Table 18. SAP_CTRL3 Register Field Descriptions
        12. 10.6.1.12 FS_MON Register (Offset = 37h) [reset = 0x00]
          1. Table 19. FS_MON Register Field Descriptions
        13. 10.6.1.13 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
          1. Table 20. BCK_MON Register Field Descriptions
        14. 10.6.1.14 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
          1. Table 21. CLKDET_STATUS Register Field Descriptions
        15. 10.6.1.15 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
          1. Table 22. DSP_PGM_MODE Register Field Descriptions
        16. 10.6.1.16 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
          1. Table 23. DSP_CTRL Register Field Descriptions
        17. 10.6.1.17 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
          1. Table 24. DIG_VOL Register Field Descriptions
        18. 10.6.1.18 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
          1. Table 25. DIG_VOL_CTRL1 Register Field Descriptions
        19. 10.6.1.19 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
          1. Table 26. DIG_VOL_CTRL2 Register Field Descriptions
        20. 10.6.1.20 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
          1. Table 27. AUTO_MUTE_CTRL Register Field Descriptions
        21. 10.6.1.21 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
          1. Table 28. AUTO_MUTE_TIME Register Field Descriptions
        22. 10.6.1.22 ANA_CTRL Register (Offset = 53h) [reset = 0h]
          1. Table 29. ANA_CTRL Register Field Descriptions
        23. 10.6.1.23 AGAIN Register (Offset = 54h) [reset = 0x00]
          1. Table 30. AGAIN Register Field Descriptions
        24. 10.6.1.24 SPI_CLK Register (Offset = 55h) [reset = 0x00]
          1. Table 31. SPI_CLK Register Field Descriptions
        25. 10.6.1.25 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]
          1. Table 32. EEPROM_CTRL0 Register Field Descriptions
        26. 10.6.1.26 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]
          1. Table 33. EEPROM_RD_CMD Register Field Descriptions
        27. 10.6.1.27 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]
          1. Table 34. EEPROM_ADDR_START0 Register Field Descriptions
        28. 10.6.1.28 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]
          1. Table 35. EEPROM_ADDR_START1 Register Field Descriptions
        29. 10.6.1.29 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]
          1. Table 36. EEPROM_ADDR_START2 Register Field Descriptions
        30. 10.6.1.30 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]
          1. Table 37. EEPROM_BOOT_STATUS Register Field Descriptions
        31. 10.6.1.31 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]
          1. Table 38. BQ_WR_CTRL1 Register Field Descriptions
        32. 10.6.1.32 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
          1. Table 39. PVDD_ADC Register Field Descriptions
        33. 10.6.1.33 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
          1. Table 40. GPIO_CTRL Register Field Descriptions
        34. 10.6.1.34 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]
          1. Table 41. GPIO0_SEL Register Field Descriptions
        35. 10.6.1.35 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]
          1. Table 42. GPIO1_SEL Register Field Descriptions
        36. 10.6.1.36 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]
          1. Table 43. GPIO2_SEL Register Field Descriptions
        37. 10.6.1.37 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
          1. Table 44. GPIO_INPUT_SEL Register Field Descriptions
        38. 10.6.1.38 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
          1. Table 45. GPIO_OUT Register Field Descriptions
        39. 10.6.1.39 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
          1. Table 46. GPIO_OUT_INV Register Field Descriptions
        40. 10.6.1.40 DIE_ID Register (Offset = 67h) [reset = 95h]
          1. Table 47. DIE_ID Register Field Descriptions
        41. 10.6.1.41 POWER_STATE Register (Offset = 68h) [reset = 0x00]
          1. Table 48. POWER_STATE Register Field Descriptions
        42. 10.6.1.42 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
          1. Table 49. AUTOMUTE_STATE Register Field Descriptions
        43. 10.6.1.43 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
          1. Table 50. PHASE_CTRL Register Field Descriptions
        44. 10.6.1.44 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
          1. Table 51. RAMP_SS_CTRL0 Register Field Descriptions
        45. 10.6.1.45 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
          1. Table 52. SS_CTRL1 Register Field Descriptions
        46. 10.6.1.46 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
          1. Table 53. SS_CTRL2 Register Field Descriptions
        47. 10.6.1.47 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
          1. Table 54. SS_CTRL3 Register Field Descriptions
        48. 10.6.1.48 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
          1. Table 55. SS_CTRL4 Register Field Descriptions
        49. 10.6.1.49 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
          1. Table 56. CHAN_FAULT Register Field Descriptions
        50. 10.6.1.50 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
          1. Table 57. GLOBAL_FAULT1 Register Field Descriptions
        51. 10.6.1.51 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
          1. Table 58. GLOBAL_FAULT2 Register Field Descriptions
        52. 10.6.1.52 WARNING Register (Offset = 73h) [reset = 0x00]
          1. Table 59. WARNING Register Field Descriptions
        53. 10.6.1.53 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
          1. Table 60. PIN_CONTROL1 Register Field Descriptions
        54. 10.6.1.54 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
          1. Table 61. PIN_CONTROL2 Register Field Descriptions
        55. 10.6.1.55 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
          1. Table 62. MISC_CONTROL Register Field Descriptions
        56. 10.6.1.56 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
          1. Table 63. CBC_CONTROL Register Field Descriptions
        57. 10.6.1.57 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
          1. Table 64. FAULT_CLEAR Register Field Descriptions
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Inductor Selections
      2. 11.1.2 Bootstrap Capacitors
      3. 11.1.3 Power Supply Decoupling
      4. 11.1.4 Output EMI Filtering
    2. 11.2 Typical Applications
      1. 11.2.1 2.0 (Stereo BTL) System
      2. 11.2.2 Design Requirements
      3. 11.2.3 Detailed Design procedures
        1. 11.2.3.1 Step One: Hardware Integration
        2. 11.2.3.2 Step Two: Hardware Integration
        3. 11.2.3.3 Step Three: Software Integration
      4. 11.2.4 Application Curves
      5. 11.2.5 MONO (PBTL) Systems
      6. 11.2.6 Advanced 2.1 System (Two TAS5825M Devices)
      7. 11.2.7 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 DVDD Supply
    2. 12.2 PVDD Supply
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 General Guidelines for Audio Amplifiers
      2. 13.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 13.1.3 Optimizing Thermal Performance
        1. 13.1.3.1 Device, Copper, and Component Layout
        2. 13.1.3.2 Stencil Pattern
          1. 13.1.3.2.1 PCB footprint and Via Arrangement
          2. 13.1.3.2.2 Solder Stencil
    2. 13.2 Layout Example
  14. 14デバイスおよびドキュメントのサポート
    1. 14.1 デバイス・サポート
      1. 14.1.1 デバイスの項目表記
      2. 14.1.2 開発サポート
    2. 14.2 ドキュメントの更新通知を受け取る方法
    3. 14.3 コミュニティ・リソース
    4. 14.4 商標
    5. 14.5 静電気放電に関する注意事項
    6. 14.6 Glossary
  15. 15メカニカル、パッケージ、および注文情報
    1. 15.1 Package Option Addendum
      1. 15.1.1 Packaging Information
      2. 15.1.2 Tape and Reel Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

特長

  • 柔軟なオーディオ I/O
    • 32、44.1、48、88.2、96、192kHz のサンプル・レートをサポート
    • I2S、LJ、RJ、TDM、SDOUT によるオーディオ・モニタ、サブチャネル、またはエコー・キャンセル
    • 3 線式のデジタル・オーディオ・インターフェイスをサポート (MCLK 不要)
  • 高効率の Class-D 動作
    • 90% を超える電力効率、90mΩ RDSon
    • 低い静止電流:PVDD=12V で 20mA 未満
  • 複数の出力構成をサポート
    • 1.0モードで1×53W (4Ω、22V、THD+N=1%)
    • 1.0モードで1×65W (4Ω、22V、THD+N=10%)
    • 2.0モードで2×30W (8Ω、24V、THD+N=1%)
    • 2.0モードで2×38W (8Ω、24V、THD+N=10%)
  • 優れたオーディオ性能:
    • 1W、1kHz、PVDD = 12VでTHD+N ≤ 0.03%
    • SNR ≥ 110dB (A-weighted)、ICN ≤ 35µVRMS
  • 柔軟な処理機能
    • 3 バンドの高度な DRC + AGL、2 × 15 BQ
    • SFS (Sound Field Spatializer)、レベル・メータ
    • 96kHz、192kHz のプロセッサ・サンプリング
    • 動的 EQ、スマート・アンプ・アルゴリズムによる低音強調およびスピーカーの熱/エクスカーション保護
  • 柔軟な電源構成
    • PVDD: 4.5V~26.4V
    • DVDDとI/O: 1.8V~3.3V
  • 優れた自己保護機能を内蔵
    • 過電流エラー (OCE)
    • サイクル単位の電流制限
    • 過熱警告 (OTW)
    • 過熱エラー (OTE)
    • 低電圧/過電圧誤動作防止 (UVLO/OVLO)
  • システム統合が簡単
    • I2C ソフトウェア制御
    • ソリューション・サイズの低減
      • 5×5mmの小型パッケージ
      • 開ループ・デバイスと比べて少ない受動部品数
      • ほとんどのアプリケーションでは、大きな電解コンデンサや大型のインダクタが不要