SLASEQ4A October 2018 – December 2018 DAC43608 , DAC53608
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Don't Care | BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB Left aligned | Don't Care | Don't Care | ||||||||||||
W | W | W | W |
BIT | FIELD | TYPE | RESET | DESCRIPTION |
---|---|---|---|---|
15-12 | Don't Care | W | 0h | Don't Care |
11-2 | DACn_DATA[9:0] / DACn_DATA[7:0] | W | 000h |
Writing to the DACn_DATA register forces the respective DAC channel to update its active register data to the DACn_DATA. Data is MSB aligned in straight binary format and follows the format below: DAC53608: { DATA[9:0] } DAC43608: { DATA[7:0], x, x } x – Don’t care bits |
1-0 | Don't Care | W | 00 | Don't Care |