SLAZ683L February   2017  – August 2021 MSP430FR59941

 

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6.13 PMM31

PMM Module

Category

Functional

Function

Device may enter lockup state during transition from AM to LPM2/3/4

Description

The device might enter lockup state if the MODOSC is requested (e.g. triggered by ADC) or removed (e.g. end of ADC conversion) during a power mode transition from AM to LPM2/3/4 (e.g. during ISR exits or Status Register modifications).
The same behavior can appear when SMCLK is requested during a power mode transition from AM to LPM3/4.
The device will remain in a lockup state unable to respond to interrupts or continue application execution until a power cycle or external reset brings it back to reset state.

Modules which can trigger MODCLK clock requests/removals are ADC and eUSCI in I2C mode using the clock low timeout feature (e.g. SMBus, PMBus).
Modules which can trigger SMCLK clock requests are ADC, eUSCI in I2C Master mode, eUSCI in SPI Master mode and eUSCI in UART mode.

If clock requests are started by the CPU/DMA (e.g. eUSCI during SPI master transmission), they can't occur at the same time as the power mode transition and thus should not be affected. The device should only be affected when the clock request is asynchronous to the power mode transition.

Workaround

1. Avoid using the aforementioned combinations of clock requests and power mode transitions:

Use LPM0/1 instead of LPM2/3/4 when expecting asynchronous MODCLK requests and removals.

OR

Use LPM0/1/2 instead of LPM3/4 when expecting asynchronous SMCLK requests.

OR

Use LPMx.5 instead of LPM2/3/4.

OR

Use a clock different than MODCLK/SMCLK when applicable (e.g. ACLK).

2. Prevent the power mode transition from happening when an asynchronous clock request/removal is expected:

Wake-up device before a UART byte is received.

AND

Wake-up device before an asynchronous ADC trigger and stay in Active Mode until conversion is completed.

AND

Keep device in AM/LPM0/LPM1 during ADC measurement.