SPRACH6F January   2019  – September 2025 66AK2G12 , AM2431 , AM2432 , AM2434 , AM3356 , AM3357 , AM3358 , AM3359 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442 , AMIC110 , AMIC120

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Communication Protocols
    1. 2.1 PROFINET
    2. 2.2 EtherCAT
    3. 2.3 EtherNet/IP
    4. 2.4 IO-Link
    5. 2.5 Parallel Redundancy Protocol (PRP)
    6. 2.6 High-Availability Seamless Redundancy (HSR)
    7. 2.7 OPC UA
    8. 2.8 Modbus TCP/IP
  6. 3Sitara Support for 3rd Party Protocol Stacks
  7. 4Revision History

2.6 High-Availability Seamless Redundancy (HSR)

TI processors currently support 100M and 1G HSR using ICSS. The AM64x/AM243x version can support 100M/1G HSR, and AM335x/AM437x/AM57x are other ICSS enabled devices that support 100M HSR. Evaluation and production software is available through the RTOS version of the Processor SDK, or through the Linux version of the Processor SDK. The ICSS-based design supports cut through switching and further offloads the duplicate removal on receive and the maintenance of the node table.

Additional resources: