SPRACN9E september   2022  – may 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4VEN-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Jacinto 7 LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 Simulation Integrity Analysis
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Waveform Quality
        2. 3.5.3.2 Eye Quality
        3. 3.5.3.3 Delay Report
        4. 3.5.3.4 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Revision History

1.4.2 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors to VDDS_DDR and the associated ground connections. Table 1-3 contains the specification for the HS bypass capacitors and for the power connections on the PCB. Generally speaking, TI recommends:

  • Fitting as many HS bypass capacitors as possible.
  • Minimizing the distance from the bypass capacitor to the pins and balls being bypassed.
  • Using the smallest physical sized ceramic capacitors possible with the highest capacitance readily available.
  • Connecting the bypass capacitor pads to their vias using the widest traces possible and using the largest via hole size possible.
  • Minimizing via sharing. Note the limits on via sharing shown in Table 1-3.

For any additional SDRAM requirements, see the manufacturer's data sheet.

Table 1-3 High-Speed Bypass Capacitors
Number Parameter MIN TYP MAX UNIT
1 HS bypass capacitor package size(1) 0201 0402 Mils
2 Distance, HS bypass capacitor to processor being bypassed(2)(3)(4) 400 Mils
3 Processor HS bypass capacitor count per VDDS_DDR rail 12 Devices
4 Processor HS bypass capacitor total capacitance per VDDS_DDR rail 3.7 µF
5 Number of connection vias for each device power/ground ball 1 Vias
6 Trace length from processor power/ground ball to connection via(2) 35 70 Mils
7 Distance, HS bypass capacitor to DDR device being bypassed(5) 150 Mils
18 DDR device HS bypass capacitor count(6) 12 Devices
19 DDR device HS bypass capacitor total capacitance(6) 0.85 µF
10 Number of connection vias for each DDR device power/ground ball 1 Vias
11 Trace length from DDR device power/ground ball to connection via(2)(8) 35 60 Mils
12 Number of connection vias for each HS capacitor(7)(8) 2 Vias
13 Trace length from bypass capacitor to connection via(2)(8) 35 100 Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40 x 20-mil surface-mount capacitor.
(2) Closer/shorter is preferable.
(3) Measured from the nearest processor power or ground ball to the center of the capacitor package.
(4) Five of these capacitors should be located underneath the processor, among the cluster of VDDS_DDR balls. Two of these capacitors should be located underneath the processor, among the cluster of VDDS_DDR_BIAS balls.
(5) Measured from the DDR device power or ground ball to the center of the capacitor package. Refer to the guidance from the SDRAM manufacturer.
(6) Per DDR device. For more information, see the guidance from the SDRAM manufacturer.
(7) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
(8) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection, and the length from the capacitor pad to the DDR device pad should be less than 150 mils.