AES Polling Mode
Main Sequence: AES Polling Mode – Figure 30-12 shows AES polling mode. The registers used in AES polling mode follow:
- AES Data RW
Plaintext/Ciphertext 0 (AES_DATA_IN_OUT_0) registers
- AES Control (AES_CTRL)
register
- AES Hash Tag Out 0
(AES_TAG_OUT_0) register
AES Interrupt Mode
The application can use software interrupts to control the flow of Context In, Context Out, Data In, and Data Out requests. To enable these interrupts
- First, initialize the device by following the
initialization sequences described in Section 30.4.1.1 and Section 30.4.1.2.
- When the device has been initialized, the application can enable the AES module interrupts through the AES Interrupt Enable (AES_IRQENABLE) register.
- Load the input buffers, AES_DATA_IN_OUT_n, with data.
Note: If the application uses interrupt mode, an interrupt is generated for each block of processed data. To support larger data flow, DMA access mode must be used and the bits in the AES_IRQENABLE register must be cleared.
AES DMA Mode
When AES DMA mode is enabled, the AES_IRQENABLE register must be cleared. To enable the DMA to transfer data, follow these steps:
- When the AES module is initialized, configure DMA sources and channels. Refer to the Direct Memory Access (DMA) chapter for the associated AES sources.
- Configure the corresponding DMA enable and request bits in the AES System Configuration (AES_SYSCONFIG) register.
The input buffer registers, AES_DATA_IN_OUT_n, are now loaded.