The figures below show the features on the Top and Bottom side of the M2-CC3301 board, some of the features highlighted are described below:

Figure 2-1 M2-CC3301 Features

• The mounted 0 Ohm resistor can be swapped to a different position to do conducted testing with the connector on board (J1/J2), the default configuration allows use of the onboard chip antenna (refer to Figure 3-1). Alternatively there is footprint for an SMA connector (J2) onboard to replace the onboard UF.L connector (J1) for performing conducted testing measurements with a compatible coaxial cable (refer to Figure 3-2).

• There is an optional placement for a 32.768 kHz oscillator (Y2), but the CC3301 already has an internal Slow Clock. The only tradeoff of not having the oscillator (Y2) is a higher power consumption when connected to an AccessPoint.

• With the optional 2 pin header (J3) one can access or provide the 3.3V power source and the board's ground.

• The M2-CC3301 Gold finger Edge connector (J5) follows the PCIE M.2 form factor Type 2230 Key E, as such the board can be compatible with any host that has a 75-position host interface connector for type key E. Refer to Section 2.3 for more information on the pin out.

Figure 2-2 M2-CC3301 More Features

• The onboard LDO (U2) is used to derive 1.8V from the provided 3.3V.

• There is an onboard Level Shifter (U3) to receive only 1.8V for the nRESET Net signal (Active Low).

• Important to note that the "Dual Inverter Buffer with Open-Drain Output" (U4) allows the device to output the interrupt lines (Active Low) and conform to the PCI Express M.2 Specification. Since the component is Open-Drain the host platform must have a 10k pull up, pads have been provided to add the resistor (R11 for IRQ_WL, and R12 for IRQ_BLE) in case that is not true.

• There are resistors to optionally change the pin used for the "HOST_nRESET" and "IRQ_WL_toHost" Net signals (refer to Section 2.3).