SWRZ092B April 2021 – March 2022 IWR6843AOP
DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application.
IWR6843AOP ES1.0, ES2.0
MSS Boot ROM Powers on DSP, Performs a Memory Initialisation of DSP L2 and downloads the program code to L2 memory. If the user application executes the STC or DSP power cycle, memory init is triggered again, hence erasing the L2 memory contents.
The workaround for Mem init would be to perform a Dummy mem init to reset a latch within the IP while keeping the destination domain in reset. This can be done by the application using the below sequence before running STC or DSP power cycling: