4.1.2.3.4.2 Designing Voltage Loop Compensator

1. The compensation designer launches with the model of the voltage loop plant for the inverter with the current loop as shown in Figure 32.
2. Note in Build Level 2, the measured gain of the plant was lower than the modeled, hence the margins in this build are lower when using the modeled plant. With the measured response these margins will be larger and hence more stable.

NOTE

The compensation designer implements the PR and harmonic resonant controller, which are entered on the powerSUITE SYSCFG page. This allows tuning of the lead lag compensator to improve the phase margin. To tune the resonant controllers, modify the parameters on the powerSUITE page, and re-invoke the compensation designer.

A lead-lag compensator can be designed using the compensation designed to improve upon the gain and phase margins in the design.

1. Once satisfied with the compensator design, click Save Comp.
2. The compensator values are now saved into the project.
3. Close the compensation designer.
4. Return to the powerSUITE page.
5. Save by typing in Ctrl+S.