TIDUDS9B December   2017  – November 2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Conditions of Use: Assumption
        1. 2.2.1.1 Generic Assumptions
        2. 2.2.1.2 Specific Assumptions
      2. 2.2.2 Diagnostics Coverage
        1. 2.2.2.1 Dual-Channel Monitoring
        2. 2.2.2.2 Checking ISO1211 Functionality With MCU (SIL1)
        3. 2.2.2.3 Checking TPS22919 Functionality With MCU (SIL1)
        4. 2.2.2.4 Checking TPS27S100 Functionality With MCU (SIL1)
        5. 2.2.2.5 Optional Monitoring Using RDY Pin of ISO5452, ISO5852S or UCC21750 Integrated Analog-to-PWM Isolated Sensor
      3. 2.2.3 Drive State
    3. 2.3 Highlighted Products
      1. 2.3.1 ISO1211
      2. 2.3.2 TPS27S100
      3. 2.3.3 TPS22919
      4. 2.3.4 ISO5852S, ISO5452
    4. 2.4 System Design Theory
      1. 2.4.1 Digital Input Receiver for STO
      2. 2.4.2 STO_1 Signal Flow Path for Controlling VCC1
      3. 2.4.3 STO_2 Signal Flow Path
        1. 2.4.3.1 High-Side Switch for Controlling Secondary-Side Supply Voltage of Gate Driver
        2. 2.4.3.2 Powering up Secondary Side: VCC2 of Gate Driver
      4. 2.4.4 Gate Driver Design
      5. 2.4.5 STO_FB Signal Flow Path
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Getting Started Hardware
      1. 3.1.1 PCB Overview
    2. 3.2 Testing and Results
      1. 3.2.1 Logic High and Logic Low STO Thresholds
      2. 3.2.2 Validation of STO1 Signal
        1. 3.2.2.1 Propagation of STO1 to VCC1 of Gate Driver
        2. 3.2.2.2 1-ms STO Pulse Rejection
        3. 3.2.2.3 Diagnostic Pulses From MCU Interface
      3. 3.2.3 Validation of STO2 Signals
        1. 3.2.3.1 Propagation of STO2 to VCC2 of Gate Driver
        2. 3.2.3.2 1-ms Pulse Rejection
        3. 3.2.3.3 Diagnostic Pulses From MCU
        4. 3.2.3.4 Inrush Current Measurement
      4. 3.2.4 3.3-V Voltage Rail From Switcher
      5. 3.2.5 60-V Input Voltage and Reverse Polarity Protection
      6. 3.2.6 Validation of Trip Zone Functionality
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 Layer Plots
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
    1. 5.1 Trademarks
  11. 6About the Author
  12. 7Recognition
  13. 8Revision History

1.1 Key System Specifications

Table 1-1 Key System Specifications
PARAMETERVALUECOMMENT
Safety functionSTOSafe torque off per IEC 61800-5-2
Hardware fault tolerance (HFT)HFT = 1 (1oo2)
IEC 61508 SIL levelSIL 3
ISO 13849Category 3, PL e
Demand modeContinuous
SFF/DC≥ 90% (HFT = 1)Cat. 3 PL e, medium DC is ≥ 90%
PFH< 10-7The quantitative analysis is not part of this concept study
STO response time10 ms (nominal), 200 ms (maximum)The time between active low STO and gate drive output (VGS) low, which means power IGBTs are OFF. The quantitative analysis is not part of this concept study.
DTI (Diagnostics test interval)100 ms (10 Hz)The quantitative analysis is not part of this concept study. Diagnostics runs at least 10 Hz (load switch STO_1 and load switch for STO_2).
FRT (Fault response time)< 200 ms
Mission time (TM)20 years
STO input voltage range

24-V DC ±15% (nominal)

±60-V DC absolute maximum

STO input logic level, valid > 2 ms

15- to 30-V DC: STO function not engaged

< 10-V DC: STO function engaged

STO is active low logic input. Input is low-pass filtered to remove OSSD pulses. Valid STO is > 2 ms.
Support of OSSD test pulses Test pulse duration < 1 ms, maximum repetition frequency 500 HzAdded low-pass filter to remove (filter-out) the test pulses to avoid trigger STO. Diagnostics for OSSD pulses to run at 250 Hz (4-ms rate).
STO feedback (STO_FB)24-V DC, isolatedIndicates the status of the drive (safe state or normal operation) and can be used to feedback status to a safety PLC for additional diagnostics, if desired
DC supply voltage24-V DC ±15% (nominal)
Isolated gate driver supply voltages

Logic supply: 3V3 to 5 V (nominal)

Output supply: +15 V/–8 V (nominal)

It is expected that the supply rails are protected to remain below the recommended maximum operating voltage of the selected isolated gate drivers
Operating ambient temperature–40°C to 85°C
Interface to MCU3.3 V I/OSee Table 3-1 to Table 3-4