SLVS149C June   2003  – September 2015 TPS65010

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Battery Charger Electrical Characteristics
    7. 6.7 Serial Interface Timing Requirements
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Battery Charger
        1. 7.3.1.1 Autonomous Power Source Selection
        2. 7.3.1.2 Temperature Qualification
        3. 7.3.1.3 Battery Preconditioning
        4. 7.3.1.4 Battery Charge Current
        5. 7.3.1.5 Battery Voltage Regulation
        6. 7.3.1.6 Charge Termination and Recharge
        7. 7.3.1.7 Sleep Mode
        8. 7.3.1.8 PG Output
        9. 7.3.1.9 Thermal Considerations for Setting Charge Current
      2. 7.3.2 Step-Down Converters, VMAIN and VCORE
        1. 7.3.2.1 Power Save Mode Operation
        2. 7.3.2.2 Forced PWM
        3. 7.3.2.3 Dynamic Voltage Positioning
        4. 7.3.2.4 Soft Start
        5. 7.3.2.5 100% Duty Cycle Low Dropout Operation
        6. 7.3.2.6 Active Discharge When Disabled
        7. 7.3.2.7 Power Good Monitoring
        8. 7.3.2.8 Overtemperature Shutdown
      3. 7.3.3 Low-Dropout Voltage Regulators
        1. 7.3.3.1 Power Good Monitoring
        2. 7.3.3.2 Enable and Sequencing
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing
      6. 7.3.6 System Reset and Control Signals
      7. 7.3.7 Vibrator Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPS65010 Power States Description
        1. 7.4.1.1 State 1: No Power
        2. 7.4.1.2 State 2: ON
        3. 7.4.1.3 State 3: Low-Power Mode
        4. 7.4.1.4 State 4: Shutdown
    5. 7.5 Programming
      1. 7.5.1 LED2 Output
      2. 7.5.2 Interrupt Management
      3. 7.5.3 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CHGSTATUS Register (Address: 01h—Reset: 00h)
      2. 7.6.2  REGSTATUS Register (Address: 02h—Reset: 00h)
      3. 7.6.3  MASK1 Register (Address: 03h—Reset: FFh)
      4. 7.6.4  MASK2 Register (Address: 04h—Reset: FFh)
      5. 7.6.5  ACKINT1 Register (Address: 05h—Reset: 00h)
      6. 7.6.6  ACKINT2 Register (Address: 06h—Reset: 00h)
      7. 7.6.7  CHGCONFIG Register Address: 07h—Reset: 1Bh
      8. 7.6.8  LED1_ON Register (Address: 08h—Reset: 00h)
      9. 7.6.9  LED1_PER Register (Address: 09h—Reset: 00h)
      10. 7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)
      11. 7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)
      12. 7.6.12 VDCDC1 Register (Address: 0Ch—Reset: 72h/73h)
      13. 7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 68h/78h)
      14. 7.6.14 VREGS1Register (Address: 0Eh—Reset: 88h)
      15. 7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)
      16. 7.6.16 DEFGPIO Register Address: (10h—Reset: 00h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS65010 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection for the Main and the Core Converter
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 LDO1 Output Voltage Adjustment
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Linear Charger Management for Single Li-Ion or Li-Polymer Cells
  • Dual Input Ports for Charging From USB or From Wall Plug, Handles 100-mA and 500-mA USB Requirements
  • Charge Current Programmable Through External Resistor
  • 1-A, 95% Efficient Step-Down Converter for I/O and Peripheral Components (VMAIN)
  • 400-mA, 90% Efficient Step-Down Converter for Processor Core (VCORE)
  • 2x 200-mA LDOs for I/O and Peripheral Components, LDO Enable Through Bus
  • Serial Interface Compatible With I2C, Supports 100-kHz, 400-kHz Operation
  • LOW_PWR Pin to Lower or Disable Processor Core Supply Voltage in Deep Sleep Mode
  • 70-µA Quiescent Current
  • 1% Reference Voltage
  • Thermal Shutdown Protection

2 Applications

  • All Single Li-Ion Cell Operated Products Requiring Multiple Supplies Including:
    • PDA
    • Cellular and Smart Phone
    • Internet Audio Player
    • Digital Still Camera
  • Digital Radio Player
  • Split Supply DSP and µP Solutions

3 Description

The TPS65010 device is an integrated power and battery management IC for applications powered by one Li-Ion or Li-Polymer cell, and which require multiple power rails. The TPS65010 provides two highly efficient, 1.25-MHz step-down converters targeted at providing the core voltage and peripheral, I/O rails in a processor-based system. Both step-down converters enter a low-power mode at light load for maximum efficiency across the widest possible range of load currents. The TPS65010 also integrates two 200-mA LDO voltage regulators, which are enabled through the serial interface. Each LDO operates with an input voltage range from 1.8 V to 6.5 V, thus allowing them to be supplied from one of the step-down converters or directly from the battery.

The TPS65010 also has a highly integrated and flexible Li-Ion linear charger and system power management. It offers integrated USB-port and AC-adapter supply management with autonomous power-source selection, power FET and current sensor, high accuracy current and voltage regulation, charge status, and charge termination.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS65010 VQFN (48) 7.00 mm x 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Block Diagram

TPS65010 fbd_lvs149.gif

4 Revision History

Changes from B Revision (January 2005) to C Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go