Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices, the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements for high-speed ADCs. This report highlights the limiting agents associated with the clock source that adversely affect the ADC signal-to-noise performance. The performance of the ADS5483 ADC clocked with the CDCE72010 is presented and compared to ideal baseline performance. Further improvement topologies are offered, along with measured results that show the CDCE72010 can meet or exceed the required specifications at high sampling rates.