TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products, it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements for high-speed ADCs. This application report highlights the limiting agents associated with the clock source that adversely affect the ADC signal-to-noise performance. The performance of the ADS5527 ADC clocked with the CDCE62005 is shown and compared to ideal baseline performance. Additional improvement topologies are presented, along with measured results that show the CDCE62005 can meet or exceed the specifications at high sampling rates, and even at the more demanding high input frequencies.