Design Support

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The jitter on the reference clock (GTXclk) can be a very crucial factor when designing applications with the TLK2521. The TLK2521 has an internal PLL with a certain bandwidth depending on the data rate. Jitter on the Refclk with a frequency below the PLL bandwidth gets transferred into the serial output data stream while high-frequency jitter gets filtered out by the internal PLL. Additional jitter on the serial data stream reduces the data eye opening and increases the probability of generating bit errors. This document shows what kind and how much jitter can be tolerated by the TLK2521 and still achieve error free data transmission. The clock jitter transfer section investigates the impact of clock jitter on the serial transmitter while the clock jitter tolerance portion focuses on maximum clock jitter for certain applications like transmission over 36 inch of FR4 backplane.