Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the stringent requirements for high-speed ADCs. This report highlights the limiting agents associated with the clock source that adversely affect the ADC?s signal-to-noise performance. The performance of the ADS5500 ADC clocked with the CDC7005 is shown and compared to ideal baseline performance. Further improvement topologies are presented along with measured results that show the CDC7005 can meet or exceed the specifications at high sampling rates, even at the more demanding high input frequencies.