Design Support


The LMK0461x device family is the industry ’s highest performance with lowest power jitter cleaner family with dual PLLs called PLL1 and PLL2. PLL1 is a very low bandwidth PLL that uses an external VCXO as voltage control oscillator. PLL2 is a high bandwidth PLL with an integrated high performance LC oscillator. LMK04610 provides 10 differential outputs and the LMK04616 provides 16 differential outputs in addition to a pair of LVCMOS outputs. To avoid coupling between different blocks, LMK046xx devices have a number of supply pins. A number of DC-DC converters are selected to power LMK04616 and their impact on the phase noise performance of the output clocks is analyzed in this document. Although all the LAB measurement results presented in this document are taken on LMK04616 EVM, they are also applicable to the LMK04610. The device is configured to accept a 122.88-MHz input clock frequency, 122.88-MHz VCXO and all output frequencies are programmed to 122.88 MHz.